MCP55: Add TINY_BOOTBLOCK support.

Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make
the build work (but this is a good idea anyway, as it's used in
multiple files).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 968e384021666f853fc742236a5f14e83f50f309..b76da5533f52b8565ea892c83609028706091723 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -81,7 +81,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -124,7 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* Allow the HT devices to be found */
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
         }
 
         if (bist == 0)

diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index a3ea7d7f9f1629ce29a3ae6fdeec0c57f19832e5..4ec8cec9f24b78f127279f6fcab4eb15ef1bdcdb 100644 (file)
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -83,7 +83,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -125,7 +124,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* Allow the HT devices to be found. */
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
        }
 
        if (bist == 0)

diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 5036f177078282e52876cdf0d7b64b68960eeb8a..f5e9f265f3b111936df3e8f3d90f1520b235edd2 100644 (file)
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -96,7 +96,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 // Disabled until it's actually used:
 // #include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -138,7 +137,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* Allow the HT devices to be found */
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
         }
 
         if (bist == 0) {

diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 49b3e177c375878719289321a09fff5074c5a120..5c0c9ae31adb8effcbbfab7fbe5fc244cfedb535 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -78,7 +78,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
 static void sio_setup(void)
@@ -117,7 +116,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                set_bsp_node_CHtExtNodeCfgEn();
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
        }
 
        post_code(0x30);

diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 69f3eb1fe92803c0fbcba26b77b9e78a0fbf56fe..8e4067f1f07f4ac8d07e4e8c732bc5a944d3e42b 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -82,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -124,7 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* Allow the HT devices to be found */
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
        }
 
        if (bist == 0)

diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index ac3ee68857cd3b04e0fd6a0d70bfd39693c5aa86..d11117f7d104ccdd1790db0e728060cfd27f8ec4 100644 (file)
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -131,7 +131,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -189,7 +188,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* Allow the HT devices to be found */
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
        }
 
        if (bist == 0)

diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index d41067a2d2a4e2e422846d84b04db52a484f14bf..4637392cd750d917b39ebde41a8777baca74ea35 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -72,7 +72,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -118,7 +117,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* Allow the HT devices to be found */
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
         }
 
         if (bist == 0)

diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 61551a718c247ecff0b8822fd349771156b79b6a..43d4ff7e72ba37609b13bffaf58b8a23fcde9ce6 100644 (file)
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -69,7 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
 static void sio_setup(void)
@@ -117,7 +116,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                set_bsp_node_CHtExtNodeCfgEn();
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
        }
 
        post_code(0x30);

diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index dac57f977bde5017c8179bcf8bb874ac7c4cfa65..95dd659b7f7f4062b80ee2466640b9a66ccb7039 100644 (file)
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -75,7 +75,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
 static void sio_setup(void)
@@ -168,7 +167,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                set_bsp_node_CHtExtNodeCfgEn();
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
         }
 
   post_code(0x30);

diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index ab0b4220b122daa129a08a192bbd9e6973994076..0dd7297ea29ebe9b0bc1e0ed8b9bb46b2d9b8ec6 100644 (file)
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -82,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -125,7 +124,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* Allow the HT devices to be found */
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
        }
 
        if (bist == 0)

diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 550e86607a8f2dd2e7029160920c860ffbd15f3f..d5d2c4129bceabe484c0029d3cc0297c12f81b57 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -79,7 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
 static void sio_setup(void)
@@ -123,7 +122,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                set_bsp_node_CHtExtNodeCfgEn();
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
        }
 
        post_code(0x30);

diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 78a1f254c5472cdd03e8aa8e3dddec74fe49d662..af6bb2bbfcda678f69e48d322aae0e168f0f932d 100644 (file)
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -2,9 +2,14 @@ config SOUTHBRIDGE_NVIDIA_MCP55
        bool
        select HAVE_USBDEBUG
        select IOAPIC
+       select TINY_BOOTBLOCK
 
 if SOUTHBRIDGE_NVIDIA_MCP55
 
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+       string
+       default "southbridge/nvidia/mcp55/bootblock.c"
+
 config ID_SECTION_OFFSET
        hex
        default 0x80

diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c
new file mode 100644 (file)
index 0000000..e735b47
--- /dev/null
+++ b/src/southbridge/nvidia/mcp55/bootblock.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+
+static void bootblock_southbridge_init(void)
+{
+       mcp55_enable_rom();
+}

diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h
index a776eb2d092e0a46e8fea869692cb43ab4c1d02d..62a6f7a073184329603b97923525c15908bc42fe 100644 (file)
--- a/src/southbridge/nvidia/mcp55/chip.h
+++ b/src/southbridge/nvidia/mcp55/chip.h
@@ -22,6 +22,8 @@
 #ifndef MCP55_CHIP_H
 #define MCP55_CHIP_H
 
+#include <device/device.h>
+
 struct southbridge_nvidia_mcp55_config
 {
        unsigned int ide0_enable : 1;

diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index e746cb63987c9c48161ecadc83a4b9be9975180b..6199965aa9c6053c36c12d7fa81c3e929b49b739 100644 (file)
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -22,13 +22,21 @@
 #ifndef MCP55_H
 #define MCP55_H
 
-#include "chip.h"
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+       #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
+#else
+       #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
+#endif
 
 #ifndef __PRE_RAM__
+#include "chip.h"
 void mcp55_enable(device_t dev);
 extern struct pci_operations mcp55_pci_ops;
 #else
+#if !defined(__ROMCC__)
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-#endif
 void mcp55_enable_usbdebug(unsigned int port);
+#endif
+#endif
+
 #endif /* MCP55_H */

diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
index 78e587e06337e96612638d843db425bff1ca26ed..d08b1d486b6fc3f3ff80c93c7d0d98640d611a41 100644 (file)
--- a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
@@ -21,11 +21,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
-       #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
-#else
-       #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
-#endif
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include "mcp55.h"
 
 static void mcp55_enable_rom(void)
 {

diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
index e0b293c81a867066d91fdcf8b8f6efefe0a1fcd0..2e78fa1ff655a4588a7ad5208531425d37d58cfb 100644 (file)
--- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
@@ -28,12 +28,6 @@
 #include <device/pci_def.h>
 #include "mcp55.h"
 
-#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
-#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
-#else
-#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
-#endif
-
 void set_debug_port(unsigned int port)
 {
        u32 dword;