2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
6 * Copyright (C) 2006,2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 #include <arch/romcc_io.h>
28 #include <device/pci_def.h>
31 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
32 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
34 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
37 void set_debug_port(unsigned int port)
40 device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
42 /* Write the port number to 0x74[15:12]. */
43 dword = pci_read_config32(dev, 0x74);
44 dword &= ~(0xf << 12);
45 dword |= (port << 12);
46 pci_write_config32(dev, 0x74, dword);
49 void mcp55_enable_usbdebug(unsigned int port)
51 device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
53 /* Mark the requested physical USB port (1-15) as the Debug Port. */
56 /* Set the EHCI BAR address. */
57 pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
59 /* Enable access to the EHCI memory space registers. */
60 pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);