2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
6 * Copyright (C) 2006,2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
25 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
27 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
30 static void mcp55_enable_rom(void)
36 /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
38 /* default MCP55 LPC single */
39 addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0);
41 // addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0);
42 addr = PCI_DEV(0, (MCP55_DEVN_BASE+1), 0);
45 /* Set the 4MB enable bit bit */
46 byte = pci_read_config8(addr, 0x88);
48 pci_write_config8(addr, 0x88, byte);
49 byte = pci_read_config8(addr, 0x8c);
51 pci_write_config8(addr, 0x8c, byte);
52 word = pci_read_config16(addr, 0x90);
54 pci_write_config16(addr, 0x90, word);