src/mainboard/gigabyte/m57sli/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #if CONFIG_K8_REV_F_SUPPORT == 1
  23 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  24 #endif
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <device/pci_ids.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include <console/console.h>
  36 #include <usbdebug.h>
  37 #include <spd.h>
  38 #include <cpu/amd/model_fxx_rev.h>
  39 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  40 #include "northbridge/amd/amdk8/raminit.h"
  41 #include "cpu/amd/model_fxx/apic_timer.c"
  42 #include "lib/delay.c"
  43 #include "cpu/x86/lapic/boot_cpu.c"
  44 #include "northbridge/amd/amdk8/reset_test.c"
  45 #include "superio/ite/it8716f/it8716f_early_serial.c"
  46 #include "superio/ite/it8716f/it8716f_early_init.c"
  47 #include "cpu/x86/bist.h"
  48 #include "northbridge/amd/amdk8/debug.c"
  49 #include "cpu/x86/mtrr/earlymtrr.c"
  50 #include "northbridge/amd/amdk8/setup_resource_map.c"
  51 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  52
  53 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
  54 #define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
  55
  56 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  57 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  58
  59 static inline int spd_read_byte(unsigned device, unsigned address)
  60 {
  61         return smbus_read_byte(device, address);
  62 }
  63
  64 #define MCP55_MB_SETUP \
  65         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
  66         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
  67         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
  68         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
  69         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
  70         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
  71
  72 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
  73 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
  74 #include "northbridge/amd/amdk8/amdk8_f.h"
  75 #include "northbridge/amd/amdk8/incoherent_ht.c"
  76 #include "northbridge/amd/amdk8/coherent_ht.c"
  77 #include "northbridge/amd/amdk8/raminit_f.c"
  78 #include "lib/generic_sdram.c"
  79 #include "resourcemap.c"
  80 #include "cpu/amd/dualcore/dualcore.c"
  81 #include "cpu/amd/car/post_cache_as_ram.c"
  82 #include "cpu/amd/model_fxx/init_cpus.c"
  83 #include "cpu/amd/model_fxx/fidvid.c"
  84 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
  85 #include "northbridge/amd/amdk8/early_ht.c"
  86
  87 static void sio_setup(void)
  88 {
  89         uint32_t dword;
  90         uint8_t byte;
  91
  92         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
  93         byte |= 0x20;
  94         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
  95
  96         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
  97         dword |= (1<<0);
  98         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
  99
 100         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
 101         dword |= (1<<16);
 102         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 103 }
 104
 105 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 106 {
 107         static const uint16_t spd_addr [] = {
 108                 // Node 0
 109                 DIMM0, DIMM2, 0, 0,
 110                 DIMM1, DIMM3, 0, 0,
 111                 // Node 1
 112                 DIMM4, DIMM6, 0, 0,
 113                 DIMM5, DIMM7, 0, 0,
 114         };
 115
 116         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 117                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 118         int needs_reset = 0;
 119         unsigned bsp_apicid = 0;
 120         uint8_t tmp = 0;
 121
 122         if (!cpu_init_detectedx && boot_cpu()) {
 123                 /* Nothing special needs to be done to find bus 0 */
 124                 /* Allow the HT devices to be found */
 125                 enumerate_ht_chain();
 126                 sio_setup();
 127                 mcp55_enable_rom();
 128         }
 129
 130         if (bist == 0)
 131                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 132
 133         pnp_enter_ext_func_mode(SERIAL_DEV);
 134         /* The following line will set CLKIN to 24 MHz, external */
 135         pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
 136         tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
 137         /* Is serial flash enabled? Then enable writing to serial flash. */
 138         if (tmp & 0x0e) {
 139                 pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
 140                 pnp_set_logical_device(GPIO_DEV);
 141                 /* Set Serial Flash interface to 0x0820 */
 142                 pnp_write_config(GPIO_DEV, 0x64, 0x08);
 143                 pnp_write_config(GPIO_DEV, 0x65, 0x20);
 144         }
 145         it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 146         pnp_exit_ext_func_mode(SERIAL_DEV);
 147
 148         setup_mb_resource_map();
 149
 150         uart_init();
 151
 152         /* Halt if there was a built in self test failure */
 153         report_bist_failure(bist);
 154
 155 #if CONFIG_USBDEBUG
 156         mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 157         early_usbdebug_init();
 158 #endif
 159         console_init();
 160         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 161
 162         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 163
 164 #if CONFIG_MEM_TRAIN_SEQ == 1
 165         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 166 #endif
 167         setup_coherent_ht_domain(); // routing table and start other core0
 168
 169         wait_all_core0_started();
 170 #if CONFIG_LOGICAL_CPUS==1
 171         // It is said that we should start core1 after all core0 launched
 172         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 173          * So here need to make sure last core0 is started, esp for two way system,
 174          * (there may be apic id conflicts in that case)
 175          */
 176         start_other_cores();
 177         wait_all_other_cores_started(bsp_apicid);
 178 #endif
 179
 180         /* it will set up chains and store link pair for optimization later */
 181         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 182
 183 #if CONFIG_SET_FIDVID
 184         {
 185                 msr_t msr;
 186                 msr=rdmsr(0xc0010042);
 187                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 188         }
 189         enable_fid_change();
 190         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 191         init_fidvid_bsp(bsp_apicid);
 192         // show final fid and vid
 193         {
 194                 msr_t msr;
 195                 msr=rdmsr(0xc0010042);
 196                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 197         }
 198 #endif
 199
 200         init_timer(); // Need to use TMICT to synconize FID/VID
 201
 202         needs_reset |= optimize_link_coherent_ht();
 203         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 204         needs_reset |= mcp55_early_setup_x();
 205
 206         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 207         if (needs_reset) {
 208                 print_info("ht reset -\n");
 209                 soft_reset();
 210         }
 211         allow_all_aps_stop(bsp_apicid);
 212
 213         //It's the time to set ctrl in sysinfo now;
 214         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 215
 216         enable_smbus();
 217
 218         /* all ap stopped? */
 219
 220         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 221
 222         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 223 }