src/mainboard/supermicro/h8qme_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #define FAM10_SCAN_PCI_BUS 0
  23 #define FAM10_ALLOCATE_IO_RANGE 1
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <device/pci_def.h>
  28 #include <device/pci_ids.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33 #include <console/console.h>
  34 #include <lib.h>
  35 #include <spd.h>
  36 #include <cpu/amd/model_10xxx_rev.h>
  37 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
  38 #include "northbridge/amd/amdfam10/raminit.h"
  39 #include "northbridge/amd/amdfam10/amdfam10.h"
  40 #include "cpu/amd/model_10xxx/apic_timer.c"
  41 #include "lib/delay.c"
  42 #include "cpu/x86/lapic/boot_cpu.c"
  43 #include "northbridge/amd/amdfam10/reset_test.c"
  44 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  45 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  46 #include "cpu/x86/bist.h"
  47 #include "northbridge/amd/amdfam10/debug.c"
  48 #include "cpu/x86/mtrr/earlymtrr.c"
  49 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  50 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  51
  52 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  53
  54 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  55 {
  56 #define SMBUS_SWITCH1 0x70
  57 #define SMBUS_SWITCH2 0x72
  58         smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
  59         smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
  60 }
  61
  62 static inline int spd_read_byte(unsigned device, unsigned address)
  63 {
  64         return smbus_read_byte(device, address);
  65 }
  66
  67 #include "northbridge/amd/amdfam10/amdfam10.h"
  68 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
  69 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
  70 #include "resourcemap.c"
  71 #include "cpu/amd/quadcore/quadcore.c"
  72 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
  73 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
  74 #include "cpu/amd/car/post_cache_as_ram.c"
  75 #include "cpu/amd/microcode/microcode.c"
  76 #include "cpu/amd/model_10xxx/update_microcode.c"
  77 #include "cpu/amd/model_10xxx/init_cpus.c"
  78 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
  79 #include "northbridge/amd/amdfam10/early_ht.c"
  80
  81 static void sio_setup(void)
  82 {
  83         uint32_t dword;
  84         uint8_t byte;
  85         enable_smbus();
  86 //      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
  87         smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
  88
  89         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
  90         byte |= 0x20;
  91         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
  92
  93         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
  94         dword |= (1<<0);
  95         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
  96
  97         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
  98         dword |= (1<<16);
  99         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 100 }
 101
 102 static const u8 spd_addr[] = {
 103         //first node
 104         RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
 105 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 106         //second node
 107         RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
 108 #endif
 109 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 110         //third node
 111         RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
 112         //forth node
 113         RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
 114 #endif
 115 };
 116
 117 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
 118 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
 119 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
 120
 121 static void write_GPIO(void)
 122 {
 123         pnp_enter_ext_func_mode(GPIO1_DEV);
 124         pnp_set_logical_device(GPIO1_DEV);
 125         pnp_write_config(GPIO1_DEV, 0x30, 0x01);
 126         pnp_write_config(GPIO1_DEV, 0x60, 0x00);
 127         pnp_write_config(GPIO1_DEV, 0x61, 0x00);
 128         pnp_write_config(GPIO1_DEV, 0x62, 0x00);
 129         pnp_write_config(GPIO1_DEV, 0x63, 0x00);
 130         pnp_write_config(GPIO1_DEV, 0x70, 0x00);
 131         pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
 132         pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
 133         pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
 134         pnp_exit_ext_func_mode(GPIO1_DEV);
 135
 136         pnp_enter_ext_func_mode(GPIO2_DEV);
 137         pnp_set_logical_device(GPIO2_DEV);
 138         pnp_write_config(GPIO2_DEV, 0x30, 0x01);
 139         pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
 140         pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
 141         pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
 142         pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
 143         pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
 144         pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
 145         pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
 146         pnp_exit_ext_func_mode(GPIO2_DEV);
 147
 148         pnp_enter_ext_func_mode(GPIO3_DEV);
 149         pnp_set_logical_device(GPIO3_DEV);
 150         pnp_write_config(GPIO3_DEV, 0x30, 0x00);
 151         pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
 152         pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
 153         pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
 154         pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
 155         pnp_exit_ext_func_mode(GPIO3_DEV);
 156 }
 157
 158 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 159 {
 160         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 161                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 162         u32 bsp_apicid = 0, val, wants_reset;
 163         msr_t msr;
 164
 165         if (!cpu_init_detectedx && boot_cpu()) {
 166                 /* Nothing special needs to be done to find bus 0 */
 167                 /* Allow the HT devices to be found */
 168                 set_bsp_node_CHtExtNodeCfgEn();
 169                 enumerate_ht_chain();
 170                 sio_setup();
 171                 mcp55_enable_rom();
 172         }
 173
 174   post_code(0x30);
 175
 176         if (bist == 0)
 177                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 178
 179   post_code(0x32);
 180
 181         pnp_enter_ext_func_mode(SERIAL_DEV);
 182         pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 183         w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 184         pnp_exit_ext_func_mode(SERIAL_DEV);
 185
 186         uart_init();
 187         console_init();
 188         write_GPIO();
 189         printk(BIOS_DEBUG, "\n");
 190
 191         /* Halt if there was a built in self test failure */
 192         report_bist_failure(bist);
 193
 194  val = cpuid_eax(1);
 195  printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 196  printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 197  printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
 198  printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 199
 200  /* Setup sysinfo defaults */
 201  set_sysinfo_in_ram(0);
 202
 203  update_microcode(val);
 204  post_code(0x33);
 205
 206  cpuSetAMDMSR();
 207  post_code(0x34);
 208
 209  amd_ht_init(sysinfo);
 210  post_code(0x35);
 211
 212  /* Setup nodes PCI space and start core 0 AP init. */
 213  finalize_node_setup(sysinfo);
 214
 215  /* Setup any mainboard PCI settings etc. */
 216  setup_mb_resource_map();
 217  post_code(0x36);
 218
 219  /* wait for all the APs core0 started by finalize_node_setup. */
 220  /* FIXME: A bunch of cores are going to start output to serial at once.
 221   * It would be nice to fixup prink spinlocks for ROM XIP mode.
 222   * I think it could be done by putting the spinlock flag in the cache
 223   * of the BSP located right after sysinfo.
 224   */
 225
 226         wait_all_core0_started();
 227 #if CONFIG_LOGICAL_CPUS==1
 228  /* Core0 on each node is configured. Now setup any additional cores. */
 229  printk(BIOS_DEBUG, "start_other_cores()\n");
 230         start_other_cores();
 231  post_code(0x37);
 232         wait_all_other_cores_started(bsp_apicid);
 233 #endif
 234
 235  post_code(0x38);
 236
 237 #if CONFIG_SET_FIDVID
 238  msr = rdmsr(0xc0010071);
 239  printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 240
 241  /* FIXME: The sb fid change may survive the warm reset and only
 242   * need to be done once.*/
 243
 244         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 245  post_code(0x39);
 246
 247  if (!warm_reset_detect(0)) {      // BSP is node 0
 248    init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 249  } else {
 250    init_fidvid_stage2(bsp_apicid, 0);  // BSP is node 0
 251         }
 252
 253  post_code(0x3A);
 254
 255  /* show final fid and vid */
 256  msr=rdmsr(0xc0010071);
 257  printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 258 #endif
 259
 260         init_timer(); // Need to use TMICT to synconize FID/VID
 261
 262  wants_reset = mcp55_early_setup_x();
 263
 264  /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 265  if (!warm_reset_detect(0)) {
 266    print_info("...WARM RESET...\n\n\n");
 267                 soft_reset();
 268    die("After soft_reset_x - shouldn't see this message!!!\n");
 269         }
 270
 271  if (wants_reset)
 272    printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 273
 274  post_code(0x3B);
 275
 276 /* It's the time to set ctrl in sysinfo now; */
 277 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 278 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 279
 280 post_code(0x3D);
 281
 282 //printk(BIOS_DEBUG, "enable_smbus()\n");
 283 //        enable_smbus(); /* enable in sio_setup */
 284
 285 post_code(0x40);
 286
 287  printk(BIOS_DEBUG, "raminit_amdmct()\n");
 288  raminit_amdmct(sysinfo);
 289  post_code(0x41);
 290
 291 // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 292  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
 293  post_code(0x42);  // Should never see this post code.
 294 }