1 Classic Timing Analyzer report for dt
2 Fri Dec 17 10:10:42 2010
3 Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
10 2. Classic Timing Analyzer Deprecation
11 3. Timing Analyzer Summary
12 4. Timing Analyzer Settings
13 5. Clock Settings Summary
14 6. Parallel Compilation
15 7. Clock Setup: 'sys_clk'
19 11. Timing Analyzer Messages
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42 ---------------------------------------
43 ; Classic Timing Analyzer Deprecation ;
44 ---------------------------------------
45 Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
48 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
49 ; Timing Analyzer Summary ;
50 +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
51 ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
52 +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
53 ; Worst-case tsu ; N/A ; None ; 16.692 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; -- ; sys_clk ; 0 ;
54 ; Worst-case tco ; N/A ; None ; 8.362 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ;
55 ; Worst-case th ; N/A ; None ; -8.416 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; -- ; sys_clk ; 0 ;
56 ; Clock Setup: 'sys_clk' ; N/A ; None ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; 0 ;
57 ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
58 +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
61 +-----------------------------------------------------------------------------------------------------------------------------------------------------+
62 ; Timing Analyzer Settings ;
63 +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
64 ; Option ; Setting ; From ; To ; Entity Name ;
65 +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
66 ; Device Name ; EP1C12Q240C8 ; ; ; ;
67 ; Timing Models ; Final ; ; ; ;
68 ; Default hold multicycle ; Same as Multicycle ; ; ; ;
69 ; Cut paths between unrelated clock domains ; On ; ; ; ;
70 ; Cut off read during write signal paths ; On ; ; ; ;
71 ; Cut off feedback from I/O pins ; On ; ; ; ;
72 ; Report Combined Fast/Slow Timing ; Off ; ; ; ;
73 ; Ignore Clock Settings ; Off ; ; ; ;
74 ; Analyze latches as synchronous elements ; On ; ; ; ;
75 ; Enable Recovery/Removal analysis ; Off ; ; ; ;
76 ; Enable Clock Latency ; Off ; ; ; ;
77 ; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
78 ; Minimum Core Junction Temperature ; 0 ; ; ; ;
79 ; Maximum Core Junction Temperature ; 85 ; ; ; ;
80 ; Number of source nodes to report per destination node ; 10 ; ; ; ;
81 ; Number of destination nodes to report ; 10 ; ; ; ;
82 ; Number of paths to report ; 200 ; ; ; ;
83 ; Report Minimum Timing Checks ; Off ; ; ; ;
84 ; Use Fast Timing Models ; Off ; ; ; ;
85 ; Report IO Paths Separately ; Off ; ; ; ;
86 ; Perform Multicorner Analysis ; Off ; ; ; ;
87 ; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
88 ; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ;
89 ; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ;
90 ; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
91 +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
94 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
95 ; Clock Settings Summary ;
96 +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
97 ; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
98 +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
99 ; sys_clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
100 +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
103 Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
104 +-------------------------------------+
105 ; Parallel Compilation ;
106 +----------------------------+--------+
107 ; Processors ; Number ;
108 +----------------------------+--------+
109 ; Number detected on machine ; 2 ;
110 ; Maximum allowed ; 1 ;
111 +----------------------------+--------+
114 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
115 ; Clock Setup: 'sys_clk' ;
116 +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
117 ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
118 +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
119 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
120 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
121 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
122 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
123 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
124 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
125 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
126 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
127 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
128 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
129 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
130 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
131 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
132 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
133 ; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
134 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
135 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
136 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
137 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
138 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
139 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
140 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
141 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
142 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
143 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
144 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
145 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
146 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
147 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
148 ; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
149 ; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
150 ; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
151 ; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
152 ; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
153 ; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
154 ; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
155 ; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
156 ; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
157 ; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
158 ; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
159 ; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
160 ; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
161 ; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
162 ; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
163 ; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
164 ; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
165 ; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
166 ; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
167 ; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
168 ; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
169 ; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
170 ; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
171 ; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
172 ; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
173 ; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
174 ; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
175 ; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
176 ; N/A ; 48.85 MHz ( period = 20.472 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.778 ns ;
177 ; N/A ; 48.85 MHz ( period = 20.472 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.778 ns ;
178 ; N/A ; 48.85 MHz ( period = 20.472 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.778 ns ;
179 ; N/A ; 48.93 MHz ( period = 20.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.745 ns ;
180 ; N/A ; 48.93 MHz ( period = 20.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.745 ns ;
181 ; N/A ; 48.93 MHz ( period = 20.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.745 ns ;
182 ; N/A ; 49.16 MHz ( period = 20.340 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.705 ns ;
183 ; N/A ; 49.16 MHz ( period = 20.340 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.705 ns ;
184 ; N/A ; 49.16 MHz ( period = 20.340 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.705 ns ;
185 ; N/A ; 49.24 MHz ( period = 20.307 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.672 ns ;
186 ; N/A ; 49.24 MHz ( period = 20.307 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.672 ns ;
187 ; N/A ; 49.24 MHz ( period = 20.307 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.672 ns ;
188 ; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
189 ; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
190 ; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
191 ; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
192 ; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
193 ; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
194 ; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
195 ; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
196 ; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
197 ; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
198 ; N/A ; 49.72 MHz ( period = 20.112 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.418 ns ;
199 ; N/A ; 49.72 MHz ( period = 20.112 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.418 ns ;
200 ; N/A ; 49.72 MHz ( period = 20.112 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.418 ns ;
201 ; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
202 ; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
203 ; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
204 ; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
205 ; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
206 ; N/A ; 49.82 MHz ( period = 20.073 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.812 ns ;
207 ; N/A ; 49.82 MHz ( period = 20.073 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.812 ns ;
208 ; N/A ; 49.97 MHz ( period = 20.014 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.320 ns ;
209 ; N/A ; 49.97 MHz ( period = 20.014 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.320 ns ;
210 ; N/A ; 49.97 MHz ( period = 20.014 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.320 ns ;
211 ; N/A ; 49.97 MHz ( period = 20.012 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.819 ns ;
212 ; N/A ; 49.97 MHz ( period = 20.012 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.819 ns ;
213 ; N/A ; 49.98 MHz ( period = 20.008 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.688 ns ;
214 ; N/A ; 50.12 MHz ( period = 19.952 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.258 ns ;
215 ; N/A ; 50.12 MHz ( period = 19.952 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.258 ns ;
216 ; N/A ; 50.12 MHz ( period = 19.952 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.258 ns ;
217 ; N/A ; 50.16 MHz ( period = 19.938 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.736 ns ;
218 ; N/A ; 50.16 MHz ( period = 19.938 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.736 ns ;
219 ; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
220 ; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
221 ; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
222 ; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
223 ; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
224 ; N/A ; 50.55 MHz ( period = 19.781 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.461 ns ;
225 ; N/A ; 50.66 MHz ( period = 19.739 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.537 ns ;
226 ; N/A ; 50.66 MHz ( period = 19.739 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.537 ns ;
227 ; N/A ; 50.71 MHz ( period = 19.720 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
228 ; N/A ; 50.72 MHz ( period = 19.718 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.516 ns ;
229 ; N/A ; 50.72 MHz ( period = 19.718 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.516 ns ;
230 ; N/A ; 50.74 MHz ( period = 19.709 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.457 ns ;
231 ; N/A ; 50.89 MHz ( period = 19.649 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
232 ; N/A ; 50.90 MHz ( period = 19.646 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.385 ns ;
233 ; N/A ; 51.01 MHz ( period = 19.603 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.909 ns ;
234 ; N/A ; 51.01 MHz ( period = 19.603 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.909 ns ;
235 ; N/A ; 51.01 MHz ( period = 19.603 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.909 ns ;
236 ; N/A ; 51.03 MHz ( period = 19.597 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 19.277 ns ;
237 ; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
238 ; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
239 ; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
240 ; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
241 ; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
242 ; N/A ; 51.05 MHz ( period = 19.588 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.395 ns ;
243 ; N/A ; 51.06 MHz ( period = 19.585 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.950 ns ;
244 ; N/A ; 51.06 MHz ( period = 19.585 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.950 ns ;
245 ; N/A ; 51.06 MHz ( period = 19.585 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.950 ns ;
246 ; N/A ; 51.14 MHz ( period = 19.556 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.862 ns ;
247 ; N/A ; 51.14 MHz ( period = 19.556 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.862 ns ;
248 ; N/A ; 51.14 MHz ( period = 19.556 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.862 ns ;
249 ; N/A ; 51.14 MHz ( period = 19.553 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.351 ns ;
250 ; N/A ; 51.14 MHz ( period = 19.553 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.351 ns ;
251 ; N/A ; 51.15 MHz ( period = 19.550 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 19.230 ns ;
252 ; N/A ; 51.25 MHz ( period = 19.514 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.312 ns ;
253 ; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
254 ; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
255 ; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
256 ; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
257 ; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
258 ; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
259 ; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
260 ; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
261 ; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
262 ; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
263 ; N/A ; 51.36 MHz ( period = 19.471 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.777 ns ;
264 ; N/A ; 51.36 MHz ( period = 19.471 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.777 ns ;
265 ; N/A ; 51.36 MHz ( period = 19.471 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.777 ns ;
266 ; N/A ; 51.37 MHz ( period = 19.465 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.145 ns ;
267 ; N/A ; 51.42 MHz ( period = 19.447 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.186 ns ;
268 ; N/A ; 51.45 MHz ( period = 19.436 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.175 ns ;
269 ; N/A ; 51.48 MHz ( period = 19.426 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.165 ns ;
270 ; N/A ; 51.51 MHz ( period = 19.415 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.154 ns ;
271 ; N/A ; 51.70 MHz ( period = 19.343 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.649 ns ;
272 ; N/A ; 51.70 MHz ( period = 19.343 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.649 ns ;
273 ; N/A ; 51.70 MHz ( period = 19.343 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.649 ns ;
274 ; N/A ; 51.75 MHz ( period = 19.324 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.630 ns ;
275 ; N/A ; 51.75 MHz ( period = 19.324 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.630 ns ;
276 ; N/A ; 51.75 MHz ( period = 19.324 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.630 ns ;
277 ; N/A ; 51.77 MHz ( period = 19.315 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.113 ns ;
278 ; N/A ; 51.79 MHz ( period = 19.310 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.616 ns ;
279 ; N/A ; 51.79 MHz ( period = 19.310 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.616 ns ;
280 ; N/A ; 51.79 MHz ( period = 19.310 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.616 ns ;
281 ; N/A ; 51.81 MHz ( period = 19.300 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[23] ; sys_clk ; sys_clk ; None ; None ; 18.606 ns ;
282 ; N/A ; 51.81 MHz ( period = 19.300 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[23] ; sys_clk ; sys_clk ; None ; None ; 18.606 ns ;
283 ; N/A ; 51.81 MHz ( period = 19.300 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[23] ; sys_clk ; sys_clk ; None ; None ; 18.606 ns ;
284 ; N/A ; 51.82 MHz ( period = 19.298 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 19.046 ns ;
285 ; N/A ; 51.83 MHz ( period = 19.294 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.092 ns ;
286 ; N/A ; 51.92 MHz ( period = 19.261 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.000 ns ;
287 ; N/A ; 51.95 MHz ( period = 19.251 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.999 ns ;
288 ; N/A ; 51.95 MHz ( period = 19.250 ns ) ; execute_stage:exec_st|reg.alu_jump ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 18.989 ns ;
289 ; N/A ; 51.98 MHz ( period = 19.239 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.037 ns ;
290 ; N/A ; 51.98 MHz ( period = 19.239 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.037 ns ;
291 ; N/A ; 52.18 MHz ( period = 19.166 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.914 ns ;
292 ; N/A ; 52.21 MHz ( period = 19.155 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.461 ns ;
293 ; N/A ; 52.21 MHz ( period = 19.155 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.461 ns ;
294 ; N/A ; 52.21 MHz ( period = 19.155 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.461 ns ;
295 ; N/A ; 52.28 MHz ( period = 19.129 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 18.927 ns ;
296 ; N/A ; 52.35 MHz ( period = 19.104 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.469 ns ;
297 ; N/A ; 52.35 MHz ( period = 19.104 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.469 ns ;
298 ; N/A ; 52.35 MHz ( period = 19.104 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.469 ns ;
299 ; N/A ; 52.36 MHz ( period = 19.098 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.837 ns ;
300 ; N/A ; 52.44 MHz ( period = 19.071 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[1] ; sys_clk ; sys_clk ; None ; None ; 18.377 ns ;
301 ; N/A ; 52.44 MHz ( period = 19.071 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[1] ; sys_clk ; sys_clk ; None ; None ; 18.377 ns ;
302 ; N/A ; 52.44 MHz ( period = 19.071 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[1] ; sys_clk ; sys_clk ; None ; None ; 18.377 ns ;
303 ; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
304 ; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
305 ; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
306 ; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
307 ; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
308 ; N/A ; 52.52 MHz ( period = 19.042 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.849 ns ;
309 ; N/A ; 52.52 MHz ( period = 19.042 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.849 ns ;
310 ; N/A ; 52.55 MHz ( period = 19.031 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 18.337 ns ;
311 ; N/A ; 52.55 MHz ( period = 19.031 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 18.337 ns ;
312 ; N/A ; 52.55 MHz ( period = 19.031 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 18.337 ns ;
313 ; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[24] ; sys_clk ; sys_clk ; None ; None ; 18.331 ns ;
314 ; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[24] ; sys_clk ; sys_clk ; None ; None ; 18.331 ns ;
315 ; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[24] ; sys_clk ; sys_clk ; None ; None ; 18.331 ns ;
316 ; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.764 ns ;
317 ; N/A ; 52.62 MHz ( period = 19.004 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.743 ns ;
318 ; N/A ; 52.62 MHz ( period = 19.003 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 18.309 ns ;
319 ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
320 +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
323 +---------------------------------------------------------------------------------------------------------------------------+
325 +-------+--------------+------------+---------+------------------------------------------------------------------+----------+
326 ; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
327 +-------+--------------+------------+---------+------------------------------------------------------------------+----------+
328 ; N/A ; None ; 16.692 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
329 ; N/A ; None ; 16.689 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
330 ; N/A ; None ; 16.688 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
331 ; N/A ; None ; 16.686 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[15] ; sys_clk ;
332 ; N/A ; None ; 16.684 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
333 ; N/A ; None ; 16.683 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
334 ; N/A ; None ; 16.681 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
335 ; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
336 ; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
337 ; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
338 ; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
339 ; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
340 ; N/A ; None ; 14.759 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
341 ; N/A ; None ; 14.741 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
342 ; N/A ; None ; 14.741 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
343 ; N/A ; None ; 14.741 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
344 ; N/A ; None ; 14.673 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
345 ; N/A ; None ; 14.673 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
346 ; N/A ; None ; 14.394 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
347 ; N/A ; None ; 14.381 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
348 ; N/A ; None ; 14.248 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
349 ; N/A ; None ; 13.957 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
350 ; N/A ; None ; 13.957 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
351 ; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
352 ; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
353 ; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
354 ; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
355 ; N/A ; None ; 13.742 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
356 ; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
357 ; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
358 ; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
359 ; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
360 ; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
361 ; N/A ; None ; 13.380 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
362 ; N/A ; None ; 13.380 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
363 ; N/A ; None ; 13.375 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
364 ; N/A ; None ; 13.265 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
365 ; N/A ; None ; 13.205 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
366 ; N/A ; None ; 13.126 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
367 ; N/A ; None ; 13.126 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
368 ; N/A ; None ; 12.974 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
369 ; N/A ; None ; 12.974 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
370 ; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
371 ; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
372 ; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
373 ; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
374 ; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
375 ; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
376 ; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
377 ; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
378 ; N/A ; None ; 12.849 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
379 ; N/A ; None ; 12.769 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
380 ; N/A ; None ; 12.542 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
381 ; N/A ; None ; 12.384 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
382 ; N/A ; None ; 12.380 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
383 ; N/A ; None ; 12.255 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
384 ; N/A ; None ; 12.236 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
385 ; N/A ; None ; 12.158 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
386 ; N/A ; None ; 12.154 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
387 ; N/A ; None ; 12.149 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
388 ; N/A ; None ; 12.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
389 ; N/A ; None ; 12.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
390 ; N/A ; None ; 12.033 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
391 ; N/A ; None ; 12.027 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
392 ; N/A ; None ; 11.977 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
393 ; N/A ; None ; 11.927 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
394 ; N/A ; None ; 11.914 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
395 ; N/A ; None ; 11.890 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
396 ; N/A ; None ; 11.889 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
397 ; N/A ; None ; 11.881 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
398 ; N/A ; None ; 11.764 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
399 ; N/A ; None ; 11.700 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
400 ; N/A ; None ; 11.660 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
401 ; N/A ; None ; 11.555 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
402 ; N/A ; None ; 11.555 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
403 ; N/A ; None ; 11.537 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
404 ; N/A ; None ; 11.535 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
405 ; N/A ; None ; 11.318 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
406 ; N/A ; None ; 11.315 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
407 ; N/A ; None ; 11.255 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
408 ; N/A ; None ; 11.184 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
409 ; N/A ; None ; 11.144 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
410 ; N/A ; None ; 11.127 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
411 ; N/A ; None ; 11.007 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
412 ; N/A ; None ; 10.999 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
413 ; N/A ; None ; 10.955 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
414 ; N/A ; None ; 10.830 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
415 ; N/A ; None ; 10.734 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
416 ; N/A ; None ; 10.714 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
417 ; N/A ; None ; 10.601 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
418 ; N/A ; None ; 10.573 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
419 ; N/A ; None ; 10.408 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
420 ; N/A ; None ; 10.117 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
421 ; N/A ; None ; 9.756 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
422 +-------+--------------+------------+---------+------------------------------------------------------------------+----------+
425 +----------------------------------------------------------------------------------------------------------------------------------------------+
427 +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
428 ; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
429 +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
430 ; N/A ; None ; 8.362 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ;
431 +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
434 +----------------------------------------------------------------------------------------------------------------------------------+
436 +---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
437 ; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
438 +---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
439 ; N/A ; None ; -8.416 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
440 ; N/A ; None ; -9.704 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
441 ; N/A ; None ; -10.065 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
442 ; N/A ; None ; -10.356 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
443 ; N/A ; None ; -10.521 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
444 ; N/A ; None ; -10.549 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
445 ; N/A ; None ; -10.662 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
446 ; N/A ; None ; -10.682 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
447 ; N/A ; None ; -10.778 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
448 ; N/A ; None ; -10.903 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
449 ; N/A ; None ; -10.947 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
450 ; N/A ; None ; -10.955 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
451 ; N/A ; None ; -11.075 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
452 ; N/A ; None ; -11.092 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
453 ; N/A ; None ; -11.132 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
454 ; N/A ; None ; -11.203 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
455 ; N/A ; None ; -11.263 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
456 ; N/A ; None ; -11.266 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
457 ; N/A ; None ; -11.483 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
458 ; N/A ; None ; -11.485 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
459 ; N/A ; None ; -11.503 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
460 ; N/A ; None ; -11.503 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
461 ; N/A ; None ; -11.608 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
462 ; N/A ; None ; -11.648 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
463 ; N/A ; None ; -11.662 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
464 ; N/A ; None ; -11.662 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[15] ; sys_clk ;
465 ; N/A ; None ; -11.663 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
466 ; N/A ; None ; -11.664 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
467 ; N/A ; None ; -11.665 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
468 ; N/A ; None ; -11.712 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
469 ; N/A ; None ; -11.829 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
470 ; N/A ; None ; -11.837 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
471 ; N/A ; None ; -11.838 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
472 ; N/A ; None ; -11.862 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
473 ; N/A ; None ; -11.875 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
474 ; N/A ; None ; -11.925 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
475 ; N/A ; None ; -11.975 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
476 ; N/A ; None ; -11.981 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
477 ; N/A ; None ; -12.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
478 ; N/A ; None ; -12.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
479 ; N/A ; None ; -12.097 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
480 ; N/A ; None ; -12.102 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
481 ; N/A ; None ; -12.106 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
482 ; N/A ; None ; -12.184 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
483 ; N/A ; None ; -12.203 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
484 ; N/A ; None ; -12.328 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
485 ; N/A ; None ; -12.332 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
486 ; N/A ; None ; -12.490 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
487 ; N/A ; None ; -12.717 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
488 ; N/A ; None ; -12.797 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
489 ; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
490 ; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
491 ; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
492 ; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
493 ; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
494 ; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
495 ; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
496 ; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
497 ; N/A ; None ; -12.922 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
498 ; N/A ; None ; -12.922 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
499 ; N/A ; None ; -12.945 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
500 ; N/A ; None ; -13.074 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
501 ; N/A ; None ; -13.074 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
502 ; N/A ; None ; -13.213 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
503 ; N/A ; None ; -13.323 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
504 ; N/A ; None ; -13.328 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
505 ; N/A ; None ; -13.328 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
506 ; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
507 ; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
508 ; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
509 ; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
510 ; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
511 ; N/A ; None ; -13.690 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
512 ; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
513 ; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
514 ; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
515 ; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
516 ; N/A ; None ; -13.905 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
517 ; N/A ; None ; -13.905 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
518 ; N/A ; None ; -14.196 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
519 ; N/A ; None ; -14.329 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
520 ; N/A ; None ; -14.342 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
521 ; N/A ; None ; -14.363 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
522 ; N/A ; None ; -14.621 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
523 ; N/A ; None ; -14.621 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
524 ; N/A ; None ; -14.689 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
525 ; N/A ; None ; -14.689 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
526 ; N/A ; None ; -14.689 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
527 ; N/A ; None ; -15.078 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
528 ; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
529 ; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
530 ; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
531 ; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
532 ; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
533 +---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
536 +--------------------------+
537 ; Timing Analyzer Messages ;
538 +--------------------------+
539 Info: *******************************************************************
540 Info: Running Quartus II Classic Timing Analyzer
541 Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
542 Info: Processing started: Fri Dec 17 10:10:41 2010
543 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dt -c dt --timing_analysis_only
544 Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
545 Warning: Found pins functioning as undefined clocks and/or memory enables
546 Info: Assuming node "sys_clk" is an undefined clock
547 Info: Clock "sys_clk" has Internal fmax of 46.92 MHz between source memory "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0" and destination register "writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]" (period= 21.311 ns)
548 Info: + Longest memory to register delay is 20.617 ns
549 Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y18; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0'
550 Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y18; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a1'
551 Info: 3: + IC(1.103 ns) + CELL(0.114 ns) = 5.534 ns; Loc. = LC_X31_Y18_N3; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[1]~3'
552 Info: 4: + IC(0.437 ns) + CELL(0.114 ns) = 6.085 ns; Loc. = LC_X31_Y18_N2; Fanout = 5; COMB Node = 'execute_stage:exec_st|left_operand[1]~4'
553 Info: 5: + IC(1.249 ns) + CELL(0.114 ns) = 7.448 ns; Loc. = LC_X31_Y22_N0; Fanout = 9; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector106~0'
554 Info: 6: + IC(0.410 ns) + CELL(0.432 ns) = 8.290 ns; Loc. = LC_X31_Y22_N5; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~152COUT1_192'
555 Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 8.370 ns; Loc. = LC_X31_Y22_N6; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~147COUT1_194'
556 Info: 8: + IC(0.000 ns) + CELL(0.608 ns) = 8.978 ns; Loc. = LC_X31_Y22_N7; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~0'
557 Info: 9: + IC(0.728 ns) + CELL(0.575 ns) = 10.281 ns; Loc. = LC_X30_Y22_N7; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[3]~2COUT1_191'
558 Info: 10: + IC(0.000 ns) + CELL(0.608 ns) = 10.889 ns; Loc. = LC_X30_Y22_N8; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[4]~10'
559 Info: 11: + IC(1.603 ns) + CELL(0.114 ns) = 12.606 ns; Loc. = LC_X32_Y21_N2; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector70~0'
560 Info: 12: + IC(1.282 ns) + CELL(0.292 ns) = 14.180 ns; Loc. = LC_X31_Y17_N0; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector70~1'
561 Info: 13: + IC(0.418 ns) + CELL(0.114 ns) = 14.712 ns; Loc. = LC_X31_Y17_N5; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~0'
562 Info: 14: + IC(0.727 ns) + CELL(0.292 ns) = 15.731 ns; Loc. = LC_X30_Y17_N6; Fanout = 7; COMB Node = 'writeback_stage:writeback_st|Equal0~5'
563 Info: 15: + IC(1.590 ns) + CELL(0.292 ns) = 17.613 ns; Loc. = LC_X27_Y19_N2; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
564 Info: 16: + IC(0.182 ns) + CELL(0.114 ns) = 17.909 ns; Loc. = LC_X27_Y19_N3; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~12'
565 Info: 17: + IC(0.431 ns) + CELL(0.114 ns) = 18.454 ns; Loc. = LC_X27_Y19_N6; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
566 Info: 18: + IC(1.296 ns) + CELL(0.867 ns) = 20.617 ns; Loc. = LC_X28_Y21_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
567 Info: Total cell delay = 9.161 ns ( 44.43 % )
568 Info: Total interconnect delay = 11.456 ns ( 55.57 % )
569 Info: - Smallest clock skew is -0.007 ns
570 Info: + Shortest clock path from clock "sys_clk" to destination register is 3.187 ns
571 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
572 Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X28_Y21_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
573 Info: Total cell delay = 2.180 ns ( 68.40 % )
574 Info: Total interconnect delay = 1.007 ns ( 31.60 % )
575 Info: - Longest clock path from clock "sys_clk" to source memory is 3.194 ns
576 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
577 Info: 2: + IC(1.007 ns) + CELL(0.718 ns) = 3.194 ns; Loc. = M4K_X33_Y18; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0'
578 Info: Total cell delay = 2.187 ns ( 68.47 % )
579 Info: Total interconnect delay = 1.007 ns ( 31.53 % )
580 Info: + Micro clock to output delay of source is 0.650 ns
581 Info: + Micro setup delay of destination is 0.037 ns
582 Info: tsu for register "execute_stage:exec_st|reg.result[2]" (data pin = "sys_res", clock pin = "sys_clk") is 16.692 ns
583 Info: + Longest pin to register delay is 19.842 ns
584 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 205; PIN Node = 'sys_res'
585 Info: 2: + IC(9.460 ns) + CELL(0.292 ns) = 11.221 ns; Loc. = LC_X37_Y17_N4; Fanout = 7; COMB Node = 'execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0'
586 Info: 3: + IC(0.771 ns) + CELL(0.114 ns) = 12.106 ns; Loc. = LC_X36_Y17_N6; Fanout = 32; COMB Node = 'execute_stage:exec_st|alu:alu_inst|calc~0'
587 Info: 4: + IC(2.560 ns) + CELL(0.114 ns) = 14.780 ns; Loc. = LC_X27_Y16_N7; Fanout = 3; COMB Node = 'execute_stage:exec_st|reg.result[1]~19'
588 Info: 5: + IC(2.407 ns) + CELL(0.442 ns) = 17.629 ns; Loc. = LC_X27_Y22_N4; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|alu_result.result[2]~8'
589 Info: 6: + IC(1.606 ns) + CELL(0.607 ns) = 19.842 ns; Loc. = LC_X32_Y22_N2; Fanout = 2; REG Node = 'execute_stage:exec_st|reg.result[2]'
590 Info: Total cell delay = 3.038 ns ( 15.31 % )
591 Info: Total interconnect delay = 16.804 ns ( 84.69 % )
592 Info: + Micro setup delay of destination is 0.037 ns
593 Info: - Shortest clock path from clock "sys_clk" to destination register is 3.187 ns
594 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
595 Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X32_Y22_N2; Fanout = 2; REG Node = 'execute_stage:exec_st|reg.result[2]'
596 Info: Total cell delay = 2.180 ns ( 68.40 % )
597 Info: Total interconnect delay = 1.007 ns ( 31.60 % )
598 Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 8.362 ns
599 Info: + Longest clock path from clock "sys_clk" to source register is 3.187 ns
600 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
601 Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X40_Y20_N8; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
602 Info: Total cell delay = 2.180 ns ( 68.40 % )
603 Info: Total interconnect delay = 1.007 ns ( 31.60 % )
604 Info: + Micro clock to output delay of source is 0.224 ns
605 Info: + Longest register to pin delay is 4.951 ns
606 Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X40_Y20_N8; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
607 Info: 2: + IC(2.827 ns) + CELL(2.124 ns) = 4.951 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx'
608 Info: Total cell delay = 2.124 ns ( 42.90 % )
609 Info: Total interconnect delay = 2.827 ns ( 57.10 % )
610 Info: th for register "writeback_stage:writeback_st|extension_uart:uart|new_tx_data" (data pin = "sys_res", clock pin = "sys_clk") is -8.416 ns
611 Info: + Longest clock path from clock "sys_clk" to destination register is 3.187 ns
612 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
613 Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X27_Y19_N6; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|new_tx_data'
614 Info: Total cell delay = 2.180 ns ( 68.40 % )
615 Info: Total interconnect delay = 1.007 ns ( 31.60 % )
616 Info: + Micro hold delay of destination is 0.015 ns
617 Info: - Shortest pin to register delay is 11.618 ns
618 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 205; PIN Node = 'sys_res'
619 Info: 2: + IC(9.282 ns) + CELL(0.867 ns) = 11.618 ns; Loc. = LC_X27_Y19_N6; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|new_tx_data'
620 Info: Total cell delay = 2.336 ns ( 20.11 % )
621 Info: Total interconnect delay = 9.282 ns ( 79.89 % )
622 Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
623 Info: Peak virtual memory: 189 megabytes
624 Info: Processing ended: Fri Dec 17 10:10:42 2010
625 Info: Elapsed time: 00:00:01
626 Info: Total CPU time (on all processors): 00:00:01
projects / calu.git / blob