2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
10 use work.extension_uart_pkg.all;
12 architecture behav of extension_uart is
14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
15 signal new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
16 signal bd_rate : baud_rate_l;
21 rs232_tx_inst : rs232_tx
35 w3_uart_send(byte_t'range),
41 rs232_rx_inst : rs232_rx
55 w4_uart_receive(byte_t'range)
62 syn : process (clk, reset)
64 if (reset = RESET_VALUE) then
65 w1_st_co <= (others=>'0');
66 w2_uart_config <= (others=>'0');
67 w3_uart_send <= (others=>'0');
68 w4_uart_receive <= (others=>'0');
71 elsif rising_edge(clk) then
72 w1_st_co <= w1_st_co_nxt;
73 w2_uart_config <= w2_uart_config_nxt;
74 w3_uart_send <= w3_uart_send_nxt;
75 w4_uart_receive <= w4_uart_receive_nxt;
76 new_tx_data <= new_tx_data_nxt;
81 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
83 gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int)
85 variable tmp_data : gp_register_t;
89 w1_st_co_nxt <= w1_st_co;
90 w2_uart_config_nxt <= w2_uart_config;
91 w3_uart_send_nxt <= w3_uart_send;
92 w4_uart_receive_nxt <= w4_uart_receive;
94 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
95 tmp_data := (others =>'0');
96 if ext_reg.byte_en(0) = '1' then
97 tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
99 if ext_reg.byte_en(1) = '1' then
100 tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
102 if ext_reg.byte_en(2) = '1' then
103 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
105 if ext_reg.byte_en(3) = '1' then
106 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
109 case ext_reg.addr(1 downto 0) is
111 w1_st_co_nxt <= tmp_data;
113 w2_uart_config_nxt <= tmp_data;
115 w1_st_co_nxt(16) <= '1'; -- busy flag set
116 w3_uart_send_nxt <= tmp_data;
118 w4_uart_receive_nxt <= tmp_data;
123 if tx_rdy = '1' and tx_rdy_int = '0' then
124 w1_st_co_nxt(16) <= '0'; -- busy flag reset
129 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
131 variable tmp_data : gp_register_t;
134 if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
135 case ext_reg.addr(1 downto 0) is
137 tmp_data := (others =>'0');
138 if ext_reg.byte_en(0) = '1' then
139 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
141 if ext_reg.byte_en(1) = '1' then
142 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
144 if ext_reg.byte_en(2) = '1' then
145 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
147 if ext_reg.byte_en(3) = '1' then
148 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
150 data_out <= tmp_data;
152 tmp_data := (others =>'0');
153 if ext_reg.byte_en(0) = '1' then
154 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
156 if ext_reg.byte_en(1) = '1' then
157 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
159 if ext_reg.byte_en(2) = '1' then
160 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
162 if ext_reg.byte_en(3) = '1' then
163 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
165 data_out <= tmp_data;
167 tmp_data := (others =>'0');
168 if ext_reg.byte_en(0) = '1' then
169 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
171 if ext_reg.byte_en(1) = '1' then
172 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
174 if ext_reg.byte_en(2) = '1' then
175 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
177 if ext_reg.byte_en(3) = '1' then
178 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
180 data_out <= tmp_data;
182 tmp_data := (others =>'0');
183 if ext_reg.byte_en(0) = '1' then
184 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
186 if ext_reg.byte_en(1) = '1' then
187 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
189 if ext_reg.byte_en(2) = '1' then
190 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
192 if ext_reg.byte_en(3) = '1' then
193 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
195 data_out <= tmp_data;
199 data_out <= (others=>'0');
204 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
206 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
208 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
213 new_tx_data_nxt <= '0';
214 bd_rate <= w2_uart_config(15 downto 0);
216 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
217 case ext_reg.addr(1 downto 0) is
223 new_tx_data_nxt <= '1';
230 end process dataprocess;
234 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------