1 Classic Timing Analyzer report for dt
2 Fri Dec 17 12:27:19 2010
3 Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
10 2. Classic Timing Analyzer Deprecation
11 3. Timing Analyzer Summary
12 4. Timing Analyzer Settings
13 5. Clock Settings Summary
14 6. Parallel Compilation
15 7. Clock Setup: 'sys_clk'
19 11. Timing Analyzer Messages
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42 ---------------------------------------
43 ; Classic Timing Analyzer Deprecation ;
44 ---------------------------------------
45 Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
48 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
49 ; Timing Analyzer Summary ;
50 +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
51 ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
52 +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
53 ; Worst-case tsu ; N/A ; None ; 18.965 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; -- ; sys_clk ; 0 ;
54 ; Worst-case tco ; N/A ; None ; 10.165 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ;
55 ; Worst-case th ; N/A ; None ; -8.849 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; -- ; sys_clk ; 0 ;
56 ; Clock Setup: 'sys_clk' ; N/A ; None ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; 0 ;
57 ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
58 +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
61 +-----------------------------------------------------------------------------------------------------------------------------------------------------+
62 ; Timing Analyzer Settings ;
63 +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
64 ; Option ; Setting ; From ; To ; Entity Name ;
65 +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
66 ; Device Name ; EP1C12Q240C8 ; ; ; ;
67 ; Timing Models ; Final ; ; ; ;
68 ; Default hold multicycle ; Same as Multicycle ; ; ; ;
69 ; Cut paths between unrelated clock domains ; On ; ; ; ;
70 ; Cut off read during write signal paths ; On ; ; ; ;
71 ; Cut off feedback from I/O pins ; On ; ; ; ;
72 ; Report Combined Fast/Slow Timing ; Off ; ; ; ;
73 ; Ignore Clock Settings ; Off ; ; ; ;
74 ; Analyze latches as synchronous elements ; On ; ; ; ;
75 ; Enable Recovery/Removal analysis ; Off ; ; ; ;
76 ; Enable Clock Latency ; Off ; ; ; ;
77 ; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
78 ; Number of source nodes to report per destination node ; 10 ; ; ; ;
79 ; Number of destination nodes to report ; 10 ; ; ; ;
80 ; Number of paths to report ; 200 ; ; ; ;
81 ; Report Minimum Timing Checks ; Off ; ; ; ;
82 ; Use Fast Timing Models ; Off ; ; ; ;
83 ; Report IO Paths Separately ; Off ; ; ; ;
84 ; Perform Multicorner Analysis ; Off ; ; ; ;
85 ; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
86 ; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ;
87 ; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ;
88 ; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
89 +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
92 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
93 ; Clock Settings Summary ;
94 +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
95 ; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
96 +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
97 ; sys_clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
98 +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
101 Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
102 +-------------------------------------+
103 ; Parallel Compilation ;
104 +----------------------------+--------+
105 ; Processors ; Number ;
106 +----------------------------+--------+
107 ; Number detected on machine ; 2 ;
108 ; Maximum allowed ; 1 ;
109 +----------------------------+--------+
112 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
113 ; Clock Setup: 'sys_clk' ;
114 +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
115 ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
116 +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
117 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
118 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
119 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
120 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
121 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
122 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
123 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
124 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
125 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
126 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
127 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
128 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
129 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
130 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
131 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
132 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
133 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
134 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
135 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
136 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
137 ; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
138 ; N/A ; 46.56 MHz ( period = 21.477 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.783 ns ;
139 ; N/A ; 46.56 MHz ( period = 21.477 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.783 ns ;
140 ; N/A ; 46.56 MHz ( period = 21.477 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.783 ns ;
141 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
142 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
143 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
144 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
145 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
146 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
147 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
148 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
149 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
150 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
151 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
152 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
153 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
154 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
155 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
156 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
157 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
158 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
159 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
160 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
161 ; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
162 ; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
163 ; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
164 ; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
165 ; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
166 ; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
167 ; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
168 ; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
169 ; N/A ; 47.00 MHz ( period = 21.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.583 ns ;
170 ; N/A ; 47.00 MHz ( period = 21.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.583 ns ;
171 ; N/A ; 47.00 MHz ( period = 21.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.583 ns ;
172 ; N/A ; 47.11 MHz ( period = 21.226 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.532 ns ;
173 ; N/A ; 47.11 MHz ( period = 21.226 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.532 ns ;
174 ; N/A ; 47.11 MHz ( period = 21.226 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.532 ns ;
175 ; N/A ; 47.19 MHz ( period = 21.190 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.929 ns ;
176 ; N/A ; 47.56 MHz ( period = 21.026 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.332 ns ;
177 ; N/A ; 47.56 MHz ( period = 21.026 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.332 ns ;
178 ; N/A ; 47.56 MHz ( period = 21.026 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.332 ns ;
179 ; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
180 ; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
181 ; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
182 ; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
183 ; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
184 ; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
185 ; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
186 ; N/A ; 47.64 MHz ( period = 20.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.729 ns ;
187 ; N/A ; 47.81 MHz ( period = 20.918 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.657 ns ;
188 ; N/A ; 48.27 MHz ( period = 20.718 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.457 ns ;
189 ; N/A ; 48.45 MHz ( period = 20.640 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.955 ns ;
190 ; N/A ; 48.45 MHz ( period = 20.640 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.955 ns ;
191 ; N/A ; 48.45 MHz ( period = 20.640 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.955 ns ;
192 ; N/A ; 49.32 MHz ( period = 20.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.583 ns ;
193 ; N/A ; 49.32 MHz ( period = 20.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.583 ns ;
194 ; N/A ; 49.32 MHz ( period = 20.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.583 ns ;
195 ; N/A ; 49.37 MHz ( period = 20.256 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.562 ns ;
196 ; N/A ; 49.37 MHz ( period = 20.256 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.562 ns ;
197 ; N/A ; 49.37 MHz ( period = 20.256 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.562 ns ;
198 ; N/A ; 49.37 MHz ( period = 20.255 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.561 ns ;
199 ; N/A ; 49.37 MHz ( period = 20.255 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.561 ns ;
200 ; N/A ; 49.37 MHz ( period = 20.255 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.561 ns ;
201 ; N/A ; 49.39 MHz ( period = 20.249 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.555 ns ;
202 ; N/A ; 49.39 MHz ( period = 20.249 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.555 ns ;
203 ; N/A ; 49.39 MHz ( period = 20.249 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.555 ns ;
204 ; N/A ; 49.40 MHz ( period = 20.242 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.481 ns ;
205 ; N/A ; 49.40 MHz ( period = 20.242 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.481 ns ;
206 ; N/A ; 49.40 MHz ( period = 20.242 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.481 ns ;
207 ; N/A ; 49.46 MHz ( period = 20.220 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.959 ns ;
208 ; N/A ; 49.46 MHz ( period = 20.219 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.958 ns ;
209 ; N/A ; 49.47 MHz ( period = 20.213 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.952 ns ;
210 ; N/A ; 49.48 MHz ( period = 20.211 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.526 ns ;
211 ; N/A ; 49.48 MHz ( period = 20.211 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.526 ns ;
212 ; N/A ; 49.48 MHz ( period = 20.211 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.526 ns ;
213 ; N/A ; 49.49 MHz ( period = 20.206 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.878 ns ;
214 ; N/A ; 49.60 MHz ( period = 20.163 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.469 ns ;
215 ; N/A ; 49.60 MHz ( period = 20.163 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.469 ns ;
216 ; N/A ; 49.60 MHz ( period = 20.163 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.469 ns ;
217 ; N/A ; 49.60 MHz ( period = 20.162 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
218 ; N/A ; 49.60 MHz ( period = 20.162 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
219 ; N/A ; 49.60 MHz ( period = 20.162 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
220 ; N/A ; 49.61 MHz ( period = 20.156 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.462 ns ;
221 ; N/A ; 49.61 MHz ( period = 20.156 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.462 ns ;
222 ; N/A ; 49.61 MHz ( period = 20.156 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.462 ns ;
223 ; N/A ; 49.63 MHz ( period = 20.149 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
224 ; N/A ; 49.63 MHz ( period = 20.149 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
225 ; N/A ; 49.63 MHz ( period = 20.149 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
226 ; N/A ; 49.64 MHz ( period = 20.146 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.452 ns ;
227 ; N/A ; 49.64 MHz ( period = 20.146 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.452 ns ;
228 ; N/A ; 49.64 MHz ( period = 20.146 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.452 ns ;
229 ; N/A ; 49.71 MHz ( period = 20.118 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.866 ns ;
230 ; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
231 ; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
232 ; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
233 ; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
234 ; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
235 ; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
236 ; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
237 ; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
238 ; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
239 ; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
240 ; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
241 ; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
242 ; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
243 ; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
244 ; N/A ; 50.14 MHz ( period = 19.943 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.691 ns ;
245 ; N/A ; 50.17 MHz ( period = 19.931 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.670 ns ;
246 ; N/A ; 50.21 MHz ( period = 19.918 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.657 ns ;
247 ; N/A ; 50.22 MHz ( period = 19.911 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.150 ns ;
248 ; N/A ; 50.22 MHz ( period = 19.911 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.150 ns ;
249 ; N/A ; 50.22 MHz ( period = 19.911 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.150 ns ;
250 ; N/A ; 50.26 MHz ( period = 19.895 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.201 ns ;
251 ; N/A ; 50.26 MHz ( period = 19.895 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.201 ns ;
252 ; N/A ; 50.26 MHz ( period = 19.895 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.201 ns ;
253 ; N/A ; 50.28 MHz ( period = 19.888 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.627 ns ;
254 ; N/A ; 50.28 MHz ( period = 19.887 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.626 ns ;
255 ; N/A ; 50.30 MHz ( period = 19.881 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.620 ns ;
256 ; N/A ; 50.32 MHz ( period = 19.874 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.546 ns ;
257 ; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
258 ; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
259 ; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
260 ; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
261 ; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
262 ; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
263 ; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
264 ; N/A ; 50.36 MHz ( period = 19.859 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.598 ns ;
265 ; N/A ; 50.48 MHz ( period = 19.808 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.114 ns ;
266 ; N/A ; 50.48 MHz ( period = 19.808 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.114 ns ;
267 ; N/A ; 50.48 MHz ( period = 19.808 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.114 ns ;
268 ; N/A ; 50.58 MHz ( period = 19.772 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.511 ns ;
269 ; N/A ; 50.58 MHz ( period = 19.770 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.500 ns ;
270 ; N/A ; 50.63 MHz ( period = 19.753 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.059 ns ;
271 ; N/A ; 50.63 MHz ( period = 19.753 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.059 ns ;
272 ; N/A ; 50.63 MHz ( period = 19.753 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.059 ns ;
273 ; N/A ; 50.68 MHz ( period = 19.731 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.470 ns ;
274 ; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
275 ; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
276 ; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
277 ; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
278 ; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
279 ; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
280 ; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
281 ; N/A ; 50.72 MHz ( period = 19.718 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.457 ns ;
282 ; N/A ; 50.72 MHz ( period = 19.717 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.456 ns ;
283 ; N/A ; 50.72 MHz ( period = 19.715 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.021 ns ;
284 ; N/A ; 50.72 MHz ( period = 19.715 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.021 ns ;
285 ; N/A ; 50.72 MHz ( period = 19.715 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.021 ns ;
286 ; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
287 ; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
288 ; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
289 ; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
290 ; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
291 ; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
292 ; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
293 ; N/A ; 50.78 MHz ( period = 19.691 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.363 ns ;
294 ; N/A ; 50.86 MHz ( period = 19.660 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 18.966 ns ;
295 ; N/A ; 50.86 MHz ( period = 19.660 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 18.966 ns ;
296 ; N/A ; 50.86 MHz ( period = 19.660 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 18.966 ns ;
297 ; N/A ; 50.87 MHz ( period = 19.658 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 18.964 ns ;
298 ; N/A ; 50.87 MHz ( period = 19.658 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 18.964 ns ;
299 ; N/A ; 50.87 MHz ( period = 19.658 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 18.964 ns ;
300 ; N/A ; 50.90 MHz ( period = 19.648 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.387 ns ;
301 ; N/A ; 50.95 MHz ( period = 19.628 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.367 ns ;
302 ; N/A ; 50.97 MHz ( period = 19.621 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 19.360 ns ;
303 ; N/A ; 50.99 MHz ( period = 19.613 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.352 ns ;
304 ; N/A ; 51.05 MHz ( period = 19.587 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.326 ns ;
305 ; N/A ; 51.10 MHz ( period = 19.570 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.300 ns ;
306 ; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
307 ; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
308 ; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
309 ; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
310 ; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
311 ; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
312 ; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
313 ; N/A ; 51.44 MHz ( period = 19.440 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.179 ns ;
314 ; N/A ; 51.47 MHz ( period = 19.428 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.167 ns ;
315 ; N/A ; 51.51 MHz ( period = 19.413 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.152 ns ;
316 ; N/A ; 51.55 MHz ( period = 19.400 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[7] ; sys_clk ; sys_clk ; None ; None ; 18.639 ns ;
317 ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
318 +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
321 +---------------------------------------------------------------------------------------------------------------------------+
323 +-------+--------------+------------+---------+------------------------------------------------------------------+----------+
324 ; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
325 +-------+--------------+------------+---------+------------------------------------------------------------------+----------+
326 ; N/A ; None ; 18.965 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
327 ; N/A ; None ; 18.965 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
328 ; N/A ; None ; 18.960 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
329 ; N/A ; None ; 18.960 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
330 ; N/A ; None ; 18.958 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[16] ; sys_clk ;
331 ; N/A ; None ; 17.463 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
332 ; N/A ; None ; 16.832 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
333 ; N/A ; None ; 14.582 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
334 ; N/A ; None ; 14.522 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
335 ; N/A ; None ; 14.522 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
336 ; N/A ; None ; 14.521 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
337 ; N/A ; None ; 14.516 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
338 ; N/A ; None ; 14.493 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
339 ; N/A ; None ; 14.024 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
340 ; N/A ; None ; 13.946 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
341 ; N/A ; None ; 13.872 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
342 ; N/A ; None ; 13.847 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
343 ; N/A ; None ; 13.783 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
344 ; N/A ; None ; 13.783 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
345 ; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
346 ; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
347 ; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
348 ; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
349 ; N/A ; None ; 13.711 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
350 ; N/A ; None ; 13.711 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
351 ; N/A ; None ; 13.661 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
352 ; N/A ; None ; 13.515 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
353 ; N/A ; None ; 13.515 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
354 ; N/A ; None ; 13.480 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
355 ; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
356 ; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
357 ; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
358 ; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
359 ; N/A ; None ; 13.410 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
360 ; N/A ; None ; 13.394 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
361 ; N/A ; None ; 13.358 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
362 ; N/A ; None ; 13.319 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
363 ; N/A ; None ; 13.319 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
364 ; N/A ; None ; 13.239 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
365 ; N/A ; None ; 13.166 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
366 ; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
367 ; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
368 ; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
369 ; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
370 ; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
371 ; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
372 ; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
373 ; N/A ; None ; 13.121 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
374 ; N/A ; None ; 13.109 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
375 ; N/A ; None ; 13.015 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
376 ; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
377 ; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
378 ; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
379 ; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
380 ; N/A ; None ; 12.931 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
381 ; N/A ; None ; 12.853 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
382 ; N/A ; None ; 12.826 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
383 ; N/A ; None ; 12.762 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
384 ; N/A ; None ; 12.742 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
385 ; N/A ; None ; 12.687 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
386 ; N/A ; None ; 12.680 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
387 ; N/A ; None ; 12.550 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
388 ; N/A ; None ; 12.445 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
389 ; N/A ; None ; 12.418 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
390 ; N/A ; None ; 12.396 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
391 ; N/A ; None ; 12.396 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
392 ; N/A ; None ; 12.396 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
393 ; N/A ; None ; 12.184 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
394 ; N/A ; None ; 12.152 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
395 ; N/A ; None ; 12.140 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
396 ; N/A ; None ; 12.139 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
397 ; N/A ; None ; 12.113 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
398 ; N/A ; None ; 12.113 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
399 ; N/A ; None ; 12.108 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
400 ; N/A ; None ; 11.975 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
401 ; N/A ; None ; 11.925 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
402 ; N/A ; None ; 11.648 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
403 ; N/A ; None ; 11.375 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
404 ; N/A ; None ; 11.324 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
405 ; N/A ; None ; 11.324 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
406 ; N/A ; None ; 11.234 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
407 ; N/A ; None ; 11.169 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
408 ; N/A ; None ; 11.158 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
409 ; N/A ; None ; 11.092 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
410 ; N/A ; None ; 10.824 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
411 ; N/A ; None ; 10.819 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
412 ; N/A ; None ; 10.809 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
413 ; N/A ; None ; 10.784 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
414 ; N/A ; None ; 10.648 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
415 ; N/A ; None ; 9.786 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
416 ; N/A ; None ; 9.782 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
417 ; N/A ; None ; 9.296 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
418 ; N/A ; None ; 9.295 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
419 ; N/A ; None ; 8.901 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
420 +-------+--------------+------------+---------+------------------------------------------------------------------+----------+
423 +----------------------------------------------------------------------------------------------------------------------------------------------+
425 +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
426 ; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
427 +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
428 ; N/A ; None ; 10.165 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ;
429 +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
432 +----------------------------------------------------------------------------------------------------------------------------------+
434 +---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
435 ; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
436 +---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
437 ; N/A ; None ; -8.849 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
438 ; N/A ; None ; -9.173 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
439 ; N/A ; None ; -9.243 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
440 ; N/A ; None ; -9.244 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
441 ; N/A ; None ; -9.730 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
442 ; N/A ; None ; -9.734 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
443 ; N/A ; None ; -10.596 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
444 ; N/A ; None ; -10.732 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
445 ; N/A ; None ; -10.757 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
446 ; N/A ; None ; -10.767 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
447 ; N/A ; None ; -10.772 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
448 ; N/A ; None ; -11.019 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
449 ; N/A ; None ; -11.020 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[16] ; sys_clk ;
450 ; N/A ; None ; -11.021 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
451 ; N/A ; None ; -11.021 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
452 ; N/A ; None ; -11.040 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
453 ; N/A ; None ; -11.106 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
454 ; N/A ; None ; -11.117 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
455 ; N/A ; None ; -11.182 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
456 ; N/A ; None ; -11.272 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
457 ; N/A ; None ; -11.272 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
458 ; N/A ; None ; -11.323 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
459 ; N/A ; None ; -11.327 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
460 ; N/A ; None ; -11.596 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
461 ; N/A ; None ; -11.873 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
462 ; N/A ; None ; -11.923 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
463 ; N/A ; None ; -12.056 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
464 ; N/A ; None ; -12.061 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
465 ; N/A ; None ; -12.061 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
466 ; N/A ; None ; -12.087 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
467 ; N/A ; None ; -12.088 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
468 ; N/A ; None ; -12.100 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
469 ; N/A ; None ; -12.132 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
470 ; N/A ; None ; -12.344 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
471 ; N/A ; None ; -12.344 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
472 ; N/A ; None ; -12.344 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
473 ; N/A ; None ; -12.366 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
474 ; N/A ; None ; -12.393 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
475 ; N/A ; None ; -12.498 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
476 ; N/A ; None ; -12.628 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
477 ; N/A ; None ; -12.635 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
478 ; N/A ; None ; -12.690 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
479 ; N/A ; None ; -12.710 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
480 ; N/A ; None ; -12.730 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
481 ; N/A ; None ; -12.774 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
482 ; N/A ; None ; -12.801 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
483 ; N/A ; None ; -12.879 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
484 ; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
485 ; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
486 ; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
487 ; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
488 ; N/A ; None ; -12.963 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
489 ; N/A ; None ; -13.057 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
490 ; N/A ; None ; -13.069 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
491 ; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
492 ; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
493 ; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
494 ; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
495 ; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
496 ; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
497 ; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
498 ; N/A ; None ; -13.114 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
499 ; N/A ; None ; -13.187 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
500 ; N/A ; None ; -13.267 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
501 ; N/A ; None ; -13.267 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
502 ; N/A ; None ; -13.306 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
503 ; N/A ; None ; -13.342 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
504 ; N/A ; None ; -13.358 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
505 ; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
506 ; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
507 ; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
508 ; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
509 ; N/A ; None ; -13.428 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
510 ; N/A ; None ; -13.463 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
511 ; N/A ; None ; -13.463 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
512 ; N/A ; None ; -13.609 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
513 ; N/A ; None ; -13.659 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
514 ; N/A ; None ; -13.659 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
515 ; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
516 ; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
517 ; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
518 ; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
519 ; N/A ; None ; -13.731 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
520 ; N/A ; None ; -13.731 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
521 ; N/A ; None ; -13.795 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
522 ; N/A ; None ; -13.820 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
523 ; N/A ; None ; -13.894 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
524 ; N/A ; None ; -14.441 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
525 ; N/A ; None ; -14.464 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
526 ; N/A ; None ; -14.469 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
527 ; N/A ; None ; -14.470 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
528 ; N/A ; None ; -14.470 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
529 ; N/A ; None ; -14.530 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
530 ; N/A ; None ; -15.539 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
531 +---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
534 +--------------------------+
535 ; Timing Analyzer Messages ;
536 +--------------------------+
537 Info: *******************************************************************
538 Info: Running Quartus II Classic Timing Analyzer
539 Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
540 Info: Processing started: Fri Dec 17 12:27:18 2010
541 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dt -c dt --timing_analysis_only
542 Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
543 Warning: Found pins functioning as undefined clocks and/or memory enables
544 Info: Assuming node "sys_clk" is an undefined clock
545 Info: Clock "sys_clk" has Internal fmax of 46.34 MHz between source memory "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0" and destination register "writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]" (period= 21.578 ns)
546 Info: + Longest memory to register delay is 20.884 ns
547 Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y14; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
548 Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y14; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a7'
549 Info: 3: + IC(1.221 ns) + CELL(0.114 ns) = 5.652 ns; Loc. = LC_X35_Y16_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|right_operand[7]~17'
550 Info: 4: + IC(1.274 ns) + CELL(0.114 ns) = 7.040 ns; Loc. = LC_X36_Y15_N7; Fanout = 4; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~COMBOUT'
551 Info: 5: + IC(1.641 ns) + CELL(0.423 ns) = 9.104 ns; Loc. = LC_X32_Y16_N1; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~29'
552 Info: 6: + IC(0.000 ns) + CELL(0.078 ns) = 9.182 ns; Loc. = LC_X32_Y16_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~19'
553 Info: 7: + IC(0.000 ns) + CELL(0.078 ns) = 9.260 ns; Loc. = LC_X32_Y16_N3; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~34'
554 Info: 8: + IC(0.000 ns) + CELL(0.178 ns) = 9.438 ns; Loc. = LC_X32_Y16_N4; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~54'
555 Info: 9: + IC(0.000 ns) + CELL(0.208 ns) = 9.646 ns; Loc. = LC_X32_Y16_N9; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~89'
556 Info: 10: + IC(0.000 ns) + CELL(0.679 ns) = 10.325 ns; Loc. = LC_X32_Y15_N0; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~102'
557 Info: 11: + IC(1.125 ns) + CELL(0.564 ns) = 12.014 ns; Loc. = LC_X31_Y15_N0; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[16]~102'
558 Info: 12: + IC(0.000 ns) + CELL(0.078 ns) = 12.092 ns; Loc. = LC_X31_Y15_N1; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[17]~107'
559 Info: 13: + IC(0.000 ns) + CELL(0.078 ns) = 12.170 ns; Loc. = LC_X31_Y15_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[18]~112'
560 Info: 14: + IC(0.000 ns) + CELL(0.078 ns) = 12.248 ns; Loc. = LC_X31_Y15_N3; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[19]~92'
561 Info: 15: + IC(0.000 ns) + CELL(0.178 ns) = 12.426 ns; Loc. = LC_X31_Y15_N4; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[20]~117'
562 Info: 16: + IC(0.000 ns) + CELL(0.208 ns) = 12.634 ns; Loc. = LC_X31_Y15_N9; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[25]~142'
563 Info: 17: + IC(0.000 ns) + CELL(0.679 ns) = 13.313 ns; Loc. = LC_X31_Y14_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[28]~65'
564 Info: 18: + IC(1.677 ns) + CELL(0.442 ns) = 15.432 ns; Loc. = LC_X36_Y12_N1; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~0'
565 Info: 19: + IC(1.252 ns) + CELL(0.114 ns) = 16.798 ns; Loc. = LC_X36_Y16_N7; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~1'
566 Info: 20: + IC(1.221 ns) + CELL(0.114 ns) = 18.133 ns; Loc. = LC_X36_Y15_N5; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~3'
567 Info: 21: + IC(0.418 ns) + CELL(0.114 ns) = 18.665 ns; Loc. = LC_X36_Y15_N0; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
568 Info: 22: + IC(0.182 ns) + CELL(0.114 ns) = 18.961 ns; Loc. = LC_X36_Y15_N1; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
569 Info: 23: + IC(0.182 ns) + CELL(0.114 ns) = 19.257 ns; Loc. = LC_X36_Y15_N2; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
570 Info: 24: + IC(0.760 ns) + CELL(0.867 ns) = 20.884 ns; Loc. = LC_X37_Y15_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]'
571 Info: Total cell delay = 9.931 ns ( 47.55 % )
572 Info: Total interconnect delay = 10.953 ns ( 52.45 % )
573 Info: - Smallest clock skew is -0.007 ns
574 Info: + Shortest clock path from clock "sys_clk" to destination register is 3.178 ns
575 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
576 Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X37_Y15_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]'
577 Info: Total cell delay = 2.180 ns ( 68.60 % )
578 Info: Total interconnect delay = 0.998 ns ( 31.40 % )
579 Info: - Longest clock path from clock "sys_clk" to source memory is 3.185 ns
580 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
581 Info: 2: + IC(0.998 ns) + CELL(0.718 ns) = 3.185 ns; Loc. = M4K_X33_Y14; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
582 Info: Total cell delay = 2.187 ns ( 68.67 % )
583 Info: Total interconnect delay = 0.998 ns ( 31.33 % )
584 Info: + Micro clock to output delay of source is 0.650 ns
585 Info: + Micro setup delay of destination is 0.037 ns
586 Info: tsu for register "fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25]" (data pin = "sys_res", clock pin = "sys_clk") is 18.965 ns
587 Info: + Longest pin to register delay is 22.115 ns
588 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 205; PIN Node = 'sys_res'
589 Info: 2: + IC(9.029 ns) + CELL(0.114 ns) = 10.612 ns; Loc. = LC_X38_Y14_N6; Fanout = 10; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[6]~3'
590 Info: 3: + IC(0.479 ns) + CELL(0.114 ns) = 11.205 ns; Loc. = LC_X38_Y14_N3; Fanout = 8; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[0]~20'
591 Info: 4: + IC(3.612 ns) + CELL(0.442 ns) = 15.259 ns; Loc. = LC_X29_Y17_N2; Fanout = 2; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[2]~11'
592 Info: 5: + IC(1.961 ns) + CELL(0.442 ns) = 17.662 ns; Loc. = LC_X35_Y16_N6; Fanout = 1; COMB Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|Equal0~1'
593 Info: 6: + IC(1.703 ns) + CELL(0.292 ns) = 19.657 ns; Loc. = LC_X38_Y14_N4; Fanout = 6; COMB Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|Equal0~2'
594 Info: 7: + IC(2.149 ns) + CELL(0.309 ns) = 22.115 ns; Loc. = LC_X35_Y19_N2; Fanout = 25; REG Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25]'
595 Info: Total cell delay = 3.182 ns ( 14.39 % )
596 Info: Total interconnect delay = 18.933 ns ( 85.61 % )
597 Info: + Micro setup delay of destination is 0.037 ns
598 Info: - Shortest clock path from clock "sys_clk" to destination register is 3.187 ns
599 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
600 Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X35_Y19_N2; Fanout = 25; REG Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25]'
601 Info: Total cell delay = 2.180 ns ( 68.40 % )
602 Info: Total interconnect delay = 1.007 ns ( 31.60 % )
603 Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 10.165 ns
604 Info: + Longest clock path from clock "sys_clk" to source register is 3.111 ns
605 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
606 Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X32_Y9_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
607 Info: Total cell delay = 2.180 ns ( 70.07 % )
608 Info: Total interconnect delay = 0.931 ns ( 29.93 % )
609 Info: + Micro clock to output delay of source is 0.224 ns
610 Info: + Longest register to pin delay is 6.830 ns
611 Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y9_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
612 Info: 2: + IC(4.706 ns) + CELL(2.124 ns) = 6.830 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx'
613 Info: Total cell delay = 2.124 ns ( 31.10 % )
614 Info: Total interconnect delay = 4.706 ns ( 68.90 % )
615 Info: th for register "fetch_stage:fetch_st|instr_r_addr[4]" (data pin = "sys_res", clock pin = "sys_clk") is -8.849 ns
616 Info: + Longest clock path from clock "sys_clk" to destination register is 3.178 ns
617 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
618 Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X39_Y14_N4; Fanout = 3; REG Node = 'fetch_stage:fetch_st|instr_r_addr[4]'
619 Info: Total cell delay = 2.180 ns ( 68.60 % )
620 Info: Total interconnect delay = 0.998 ns ( 31.40 % )
621 Info: + Micro hold delay of destination is 0.015 ns
622 Info: - Shortest pin to register delay is 12.042 ns
623 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 205; PIN Node = 'sys_res'
624 Info: 2: + IC(9.029 ns) + CELL(0.114 ns) = 10.612 ns; Loc. = LC_X38_Y14_N6; Fanout = 10; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[6]~3'
625 Info: 3: + IC(0.482 ns) + CELL(0.114 ns) = 11.208 ns; Loc. = LC_X38_Y14_N0; Fanout = 2; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[4]~14'
626 Info: 4: + IC(0.719 ns) + CELL(0.115 ns) = 12.042 ns; Loc. = LC_X39_Y14_N4; Fanout = 3; REG Node = 'fetch_stage:fetch_st|instr_r_addr[4]'
627 Info: Total cell delay = 1.812 ns ( 15.05 % )
628 Info: Total interconnect delay = 10.230 ns ( 84.95 % )
629 Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
630 Info: Peak virtual memory: 189 megabytes
631 Info: Processing ended: Fri Dec 17 12:27:19 2010
632 Info: Elapsed time: 00:00:01
633 Info: Total CPU time (on all processors): 00:00:01
projects / calu.git / blob