Sven Schnelle [Mon, 14 Mar 2011 08:18:27 +0000 (08:18 +0000)]
ec/acpi: make ACPI register pair configurable
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6442
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Mon, 14 Mar 2011 08:18:17 +0000 (08:18 +0000)]
ACPI EC: add ec_set_bit() / ec_clr_bit()
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6441
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Mathias Krause [Thu, 10 Mar 2011 07:52:02 +0000 (07:52 +0000)]
nvramtool: Move code so it has access to the right data structures
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6440
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Tue, 8 Mar 2011 23:01:46 +0000 (23:01 +0000)]
Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF.
The patch makes these changes:
1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15
romstage.c files where it is used (AMD family 10h projects).
2) Add a prototype to amdfam10.h.
3) Modify the swap list and test in real hardware for mahogany_fam10 and
kino family 10h and confirm HT3 operation for the SB link.
Abuild tested.
Signed-off-by: Scott Duplichan <sc...@notabs.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6439
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Tue, 8 Mar 2011 20:49:18 +0000 (20:49 +0000)]
Add option_table.h as dependency for all C based object files if option tables are used.
This is to make sure that the file exists when it is needed. While this isn't the case for every C source file, it doesn't hurt either to create the file a bit sooner than strictly necessary.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6438
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Mathias Krause [Tue, 8 Mar 2011 12:58:16 +0000 (12:58 +0000)]
nvramtool: Change precedence order for data sources
nvramtool couldn't handle certain combinations of sources for CMOS
layout and CMOS data. This change allows for nearly all combinations.
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6437
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Tue, 8 Mar 2011 07:50:43 +0000 (07:50 +0000)]
Move cmos.default handling to bootblock
The cmos.default code wasn't actually used so far, due to an oversight
when forward-porting this feature from an old branch.
- Extend walkcbfs' use by factoring out the stage handling into C code.
- New sanitize_cmos() function that looks if CMOS data is invalid and
cmos.default exists and if so overwrites CMOS with cmos.default data.
- Use sanitize_cmos() in both bootblock implementations.
- Drop the need to reboot after writing CMOS: CMOS wasn't used so far,
so we can go on without a reboot.
- Remove the restriction that cmos.default only works on CAR boards.
- Always build in cmos.default support on boards that
USE_OPTION_TABLE.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6436
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Mon, 7 Mar 2011 09:09:51 +0000 (09:09 +0000)]
X60: add thermal zone 1
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6435
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Mon, 7 Mar 2011 09:00:50 +0000 (09:00 +0000)]
X60: add thermal zone 0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6434
2b7e53f0-3cfb-0310-b3e9-
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Michael Karcher [Sun, 6 Mar 2011 17:58:31 +0000 (17:58 +0000)]
Add support for the NSC PC87364 Super I/O.
superiotool -deV output:
http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6433
2b7e53f0-3cfb-0310-b3e9-
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Jonathan Kollasch [Fri, 4 Mar 2011 20:01:15 +0000 (20:01 +0000)]
Add P-states for select Socket 754 processors.
States for AMA3000BEX5AR, SDA3100AIO3BX, and SDA3400AIO3BX
are from AMD document 30430 3.51. States for ADA3200AIO4BX
derived from SSDT of a MS-7135. States for TMDML34BKX5LD derived
from legacy PowerNow! table of a MS-7135, and therefore lack accurate
TDP information.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6432
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 4 Mar 2011 17:09:21 +0000 (17:09 +0000)]
Redo r6099 after copy&pasted code reintroduced DIMMx #defines
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6431
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Thu, 3 Mar 2011 23:09:43 +0000 (23:09 +0000)]
Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code.
With this change the last P-state entry of the last CPU in the table
is successfully conveyed into the SSDT.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6430
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Thu, 3 Mar 2011 20:52:50 +0000 (20:52 +0000)]
Improve ck804 IOAPIC and HPET resource handling.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6429
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
jakllsch [Thu, 3 Mar 2011 15:36:08 +0000 (15:36 +0000)]
Configure PCIe lanes on ms7135 as original BIOS does.
Signed-off-by: <jakllsch@kollasch.net>
Acked-by: <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6428
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Thu, 3 Mar 2011 08:29:03 +0000 (08:29 +0000)]
add PC87384 SuperIO
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6427
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Alexandru Gagniuc [Wed, 2 Mar 2011 19:56:28 +0000 (19:56 +0000)]
Fixes licensing of src/southbridge/via/k8t890/k8x8xx.h to GPLv2+ from GPLv3.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6426
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sylvain "ythier" Hitier [Tue, 1 Mar 2011 22:02:37 +0000 (22:02 +0000)]
Fix some subsystemid statements in r6421
Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6425
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sylvain "ythier" Hitier [Tue, 1 Mar 2011 21:57:11 +0000 (21:57 +0000)]
[SCONFIG] remove unused variable in inherit_subsystem_ids()
i is a leftover from debugging, no longer needed. So just remove it.
Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6424
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Tue, 1 Mar 2011 21:51:29 +0000 (21:51 +0000)]
Fix a simple whitespace error in src/include/device/device.h
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
Reported-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6423
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Tue, 1 Mar 2011 21:43:57 +0000 (21:43 +0000)]
Add lex output
lex.yy.c_shipped wasn't committed in r6420, which breaks the build
if you don't have the expert option checked that rebuilds those files.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6422
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Tue, 1 Mar 2011 19:58:47 +0000 (19:58 +0000)]
Use subsystem id from devicetree.cb instead of Kconfig and move
all boards to the new config scheme.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Tue, 1 Mar 2011 19:58:15 +0000 (19:58 +0000)]
Add subsystemid option to sconfig
Allow user to add 'subsystemid <vendor> <device> [inherit]' to devicetree.cb for
PCI and PCI domain devices.
Example:
device pci 00.0 on
subsystemid dead beef
end
If the user wants to have this ID inherited to all subdevices/functions,
he can add 'inherit', like in the following example:
device pci 00.0 on
subsystemid dead beef inherit
end
If the user don't want to inherit a Subsystem for a single device, he can
specify 'subsystemid 0 0' on this particular device.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6420
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Tue, 1 Mar 2011 08:09:22 +0000 (08:09 +0000)]
Fix double inclusion of toplevel Makefile.inc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6419
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Tue, 1 Mar 2011 07:30:14 +0000 (07:30 +0000)]
Mark non-returning function as noreturn to help some compiler versions
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6418
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Tue, 1 Mar 2011 07:26:00 +0000 (07:26 +0000)]
libpayload: Add more libpci-compatibility (#defines)
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6417
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Tue, 1 Mar 2011 07:24:53 +0000 (07:24 +0000)]
libpayload: Implement pci_cleanup()
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6416
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Tue, 1 Mar 2011 07:23:49 +0000 (07:23 +0000)]
libpayload: Implement ffs()
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6415
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 1 Mar 2011 07:13:10 +0000 (07:13 +0000)]
Some more standard types and defines (libpayload)
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6414
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Tue, 1 Mar 2011 07:12:08 +0000 (07:12 +0000)]
Add lib/ to the default library path of lpgcc, so -l works
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6413
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Mon, 28 Feb 2011 18:09:58 +0000 (18:09 +0000)]
add functions to set Subsystem Vendor/Device to rl5c746
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6412
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 03:59:34 +0000 (03:59 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6411
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 03:56:52 +0000 (03:56 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6410
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 03:53:47 +0000 (03:53 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6409
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 03:49:28 +0000 (03:49 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
In fact I changed coreDelay before deleting
the code in fidvid that called it. But there're
still a couple of calls from src/northbridge/amd/amdmct/wrappers/mcti_d.c
Since the comment encouraged fixing something, I
parametrized it with the delay time in microseconds
and paranoically tried to avoid an overflow at pathological
moments.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6408
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 03:35:43 +0000 (03:35 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
bits 13 - 15 of F3xd4 (StutterScrubEn, CacheFlushImmOnAllHalt and MTC1eEn
are reserved for revisions D0 and earlier, so whe should not set them
to 0 in fidvid.c config_clk_power_ctrl_reg0(...), called from prep_fid_change.
For revisions > D0 (when we support them) it is ok not ot clear them,
because they are documented as 0 on reset. bit 12 should be left alone
according to BKDG. Should I set 11:8 ClkRampHystSel to 0 in the mask
too, just to indicate we're touching them ? We'll OR them to 1111 anyway...
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6407
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 03:32:23 +0000 (03:32 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Well, I understand it better like this, but maybe
it's only me, part of the changes are paranoic, and
the only effective change is for a factor depending on
mobile or not that I can't test.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6406
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 03:25:07 +0000 (03:25 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Add an untested step in BKDG 2.4.2.8. I don't
have the hardware with Core Performance Boost and
I think it's only available in revision E that does
not even have a constant yet.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6405
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 03:19:17 +0000 (03:19 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Add to init_fidvid_stage2 some step
mentioned in BKDG 2.4.2.7 that was missing . Some lines
are dead code now, but may handy if one day we support
revison E CPUs.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6404
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 03:12:00 +0000 (03:12 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Add to init_fidvid_stage2 some step for my CPU (rev C3)
mentioned in BKDG 2.4.2.6 (5) that was missing
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6403
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 03:08:06 +0000 (03:08 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Looking at BKDG the process for updating
Pstate Nb vid after warn reset seemed
more similar to the codethat was there fo
pvi than the one for svi, so I called the
pvi function passing a pvi/svi flag. I don't
find documentation on why should UpdateSinglePlaneNbVid()
be called in PVI, but since I can't test it,
I leave it as it was.
This patch showed some progress beyond fidvid in my
boar,d but only sometimes, most times it just didn't
work.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6402
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 03:02:40 +0000 (03:02 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Factor out some common expressions.
Add an error message when coreboots hangs waiting for a pstate
that never comes (it happened to me), and throw some
paranoia at it for good mesure.
If I understood BKDG fam10 CPUs never need a software initiated vid transition,
because the hardware knows what to do when you just request
a Pstate change if the cpu is properly configured. In fact
unifying a little what PVI and SVI do was better for my board (SVI).
So I drop transitionVid, which I didn't understand either (why
did it have a case for PVI if it is never called for PVI ?
Why did the PVI case distinguigh cpu or nb when PVI is
theoretically single voltage plane ? ).
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6401
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marc Jones [Mon, 28 Feb 2011 02:36:15 +0000 (02:36 +0000)]
Kino devicetree.cb SIO PNP devices were not matched up with the
actual SIO. This fixes the serial device being disabled during PNP
init.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6400
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 02:33:59 +0000 (02:33 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Contemplate the possibility of nbCofVidUpdate not being
defined, trying to get closer to BKDG
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6399
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 00:31:24 +0000 (00:31 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Configuration of F3x[84:80] was hardcoded for rev B.
I change that for some code that checks for revision
and configures according to BKDG. Unfinished but
hopefully better than it was.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6398
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 00:24:21 +0000 (00:24 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
BKDG says nbSynPtrAdj may also be 6 sometimes.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6397
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 00:18:43 +0000 (00:18 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I didn't understand quite why it did that iwth F3xA0 (Power
Control Misc Register) so I moved Pll Lock time to rules in defaults.h
and reimplemented F3xA0 programming. A later patch will remove
a part I don't know what's mean to do.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6396
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 00:10:37 +0000 (00:10 +0000)]
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Bring F3xD4 (Clock/Power Control Register 0) more in line
with BKDG i more cases. It requires looking at the CPU package type
so I add a function for that (in the wrong place?) and some
new constants
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6395
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Mon, 28 Feb 2011 00:00:51 +0000 (00:00 +0000)]
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . Factor out the decision whether
to update northbridge frequency and voltage because there
was the same code in 3 places and so we can later modify it
in one place.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6394
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 27 Feb 2011 23:58:34 +0000 (23:58 +0000)]
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . Factor out the decision whether
to update northbridge frequency and voltage because there
was the same code in 3 places and so we can later modify it
in one place.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6393
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 27 Feb 2011 23:56:00 +0000 (23:56 +0000)]
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid. Factor out a little common code.
Also, our earlier config_clk_power_ctrl_reg0
was still too long and it'd get longer with forthcoming patches.
We now take apart F3xD4[PowerStepUp,PowerStepDown]
to its own function.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6392
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 27 Feb 2011 23:53:11 +0000 (23:53 +0000)]
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3x[84:80],
ACPI Power State Control Registers, to its own function.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6391
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 27 Feb 2011 23:50:30 +0000 (23:50 +0000)]
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj],
Northbridge/core synchronization FIFO pointer adjust, to its own function.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6390
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 27 Feb 2011 23:47:57 +0000 (23:47 +0000)]
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xA0,
Power Control Misc Register to its own function.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6389
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 27 Feb 2011 23:45:34 +0000 (23:45 +0000)]
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xD4,
Clock Power/Timing Control 0 to its own function.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6388
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 27 Feb 2011 23:42:58 +0000 (23:42 +0000)]
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode). No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart VSRamp in step b
of 2.4.1.7 BKDG to its own function.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6387
2b7e53f0-3cfb-0310-b3e9-
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Xavi Drudis Ferran [Sun, 27 Feb 2011 02:48:41 +0000 (02:48 +0000)]
Add 300 MHz and 500 MHz HT frequency limits
Needed to build successfully with Expert mode enabled.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6386
2b7e53f0-3cfb-0310-b3e9-
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Xavi Drudis Ferran [Sat, 26 Feb 2011 23:29:44 +0000 (23:29 +0000)]
Make AMD Fam10h CPU microcode updates optional in Expert mode
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Sat, 26 Feb 2011 19:46:08 +0000 (19:46 +0000)]
Following patch fills in the callbacks for PCIe x16 resets. This board uses GPM8,GPM9 as reset toggles.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6384
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sat, 26 Feb 2011 18:42:04 +0000 (18:42 +0000)]
Correct error in ASRock E350M1 commit that breaks build for ASRock 939a785gmh.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6383
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sat, 26 Feb 2011 17:49:49 +0000 (17:49 +0000)]
Add support for the ASRock E350M1, an AMD family 14h Fusion board.
A video option rom must be added for UMA graphics support. It can
be extracted from the supplied UEFI BIOS.
ASRock E350M1 support is based on the AMD persimmon project. The
major differences are SIO model and DIMM SDP addressing. With this
coreboot and seabios, the board can boot DOS from a SATA drive and
can boot WinPE from a USB flash drive. I was unable to get
Windows setup to run.
The board has a socketed SPI flash BIOS chip and a serial port
header. The SIO is Nuvoton NCT5572D. Using coreboot's existing
Winbond w83627hf is a good enough match to get the serial port
and keyboard working.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6382
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Sat, 26 Feb 2011 13:34:01 +0000 (13:34 +0000)]
It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG.
Signed-off-by: Rudolf Marek <r.marek@asssembler.cz>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6381
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Thu, 24 Feb 2011 14:35:42 +0000 (14:35 +0000)]
Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS
This affects the CMOS options iommu, ECC_memory, max_mem_clock,
hw_scrubber, interleave_chip_selects.
If they're absent in cmos.layout, a Kconfig value is used if it exists,
or a hardcoded default otherwise.
[Patrick: I changed the ramstage CMOS handling a bit, and dropped the
reliance of hw_scrubber on ECC RAM, as it has nothing to do with it -
it's the cache that's being scrubbed here.]
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6380
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Thu, 24 Feb 2011 13:54:10 +0000 (13:54 +0000)]
Add new option 'sata_mode' to CMOS and 'SATA_MODE' to Kconfig for AMD SB600
coreboot used to set the chipset to IDE mode unconditionally.
Now, the user has a couple of ways to choose the configuration:
- If a CMOS variable sata_mode exist, it is used to decide if IDE or
AHCI is to be used as interface.
- If not, a Kconfig option is used.
- If unchanged, the Kconfig option is set to IDE.
So unless the cmos.layout is extended or Kconfig is modified, this won't
change behaviour.
[Patrick: Compared to Josef's version, I changed the Kconfig option to
be boolean, instead of a magic string. Also, the "IDE" default is
handled in Kconfig, instead of an additional line of code.]
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6379
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 24 Feb 2011 07:43:37 +0000 (07:43 +0000)]
Tyan/s2735 doesn't need to define its own hard_reset function anymore.
The southbridge already provides hard_reset.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6378
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 24 Feb 2011 07:18:11 +0000 (07:18 +0000)]
libpayload: Move stdin/stdout/stderr away from headers
Otherwise they exist in several object files, confusing the linker
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6377
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Thu, 24 Feb 2011 05:00:33 +0000 (05:00 +0000)]
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6376
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 22 Feb 2011 14:35:05 +0000 (14:35 +0000)]
Move coreboot specific rules and setup to toplevel Makefile.inc
KERNELVERSION issue found by Stefan is fixed.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6375
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Mon, 21 Feb 2011 09:39:17 +0000 (09:39 +0000)]
[i945] Add SPD adress mapping
The current code works only with dual channel if Channel 0 uses SPD address
0x50/0x51, while the second channel has to use 0x52/0x53.
For hardware that uses other addresses (like the ThinkPad X60) this means we
get only one module running instead of both.
This patch adds a second parameter to sdram_initialize, which is an array with
2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single
DIMM socket. If NULL is given as the second parameter, the code uses the old
addressing scheme.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6374
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Sat, 19 Feb 2011 14:51:31 +0000 (14:51 +0000)]
It turns out that the code which enables specific LDN is somewhat buggy.
Instead of enable the device the device gets disabled. However after some time the serial line gets back, most likely some "enable resources" might fix it.
I'm attaching patch which somewhat fixes the problem and changes the function to look same in all superio code. Some boards even did not convert the dev->enabled to 0,1 values.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6373
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 17 Feb 2011 20:48:45 +0000 (20:48 +0000)]
Handle compiler options for source classes more generically
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6372
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 17 Feb 2011 20:47:49 +0000 (20:47 +0000)]
Make Makefile.inc parser loop more generic
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6371
2b7e53f0-3cfb-0310-b3e9-
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David Hendricks [Thu, 17 Feb 2011 00:52:02 +0000 (00:52 +0000)]
add mec1308 support to superiotool
This patch also disables FDC37M81x since it has a conflicting device ID
and is not supported very well anyway.
Signed-off-by: David Hendricks <dhendrix@google.com>
Acked-by: Stefan Reinauer <reinauer@google.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6370
2b7e53f0-3cfb-0310-b3e9-
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Alexandru Gagniuc [Wed, 16 Feb 2011 17:40:04 +0000 (17:40 +0000)]
Fix build errors introduced in r6367
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6369
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Wed, 16 Feb 2011 15:04:59 +0000 (15:04 +0000)]
Add ACPI code for Lenvo X60
It currently supports:
- Sleepbutton
- AC state
- Battery state
- Interrupt routing
- Display Brightness control
- Hotkeys
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6368
2b7e53f0-3cfb-0310-b3e9-
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Alexandru Gagniuc [Wed, 16 Feb 2011 13:43:00 +0000 (13:43 +0000)]
Extended K8T890 driver to include the K8T800 and K8M800 northbridges
The K8T800 is almost identical to the K8T800Pro, also added to this patch.
The K8T800_OLD is also defined, which is an older version of the K8T800,
but which has no driver and early HT code yet. Also extended the K8M890 VGA
driver to work for the K8M800 (not tested). According to the datasheet, the
K8T890 and K8T800 are similar enough to be able to use the same
initialization code. At least for the K8T800, this is sufficient to have
a working HT link with the CPU, and to initialise the V-Link to the
southbridge.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6367
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Wed, 16 Feb 2011 13:12:41 +0000 (13:12 +0000)]
Lenovo ThinkPad X60: Enable SMI handler
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6366
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Tue, 15 Feb 2011 13:07:32 +0000 (13:07 +0000)]
Remove more files and lines mistakenly copied from Roda to X60
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6365
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Tue, 15 Feb 2011 11:14:17 +0000 (11:14 +0000)]
Remove ACPI mistakenly copied from Roda to ThinkPad X60
It is incorrect, and will be replaced with proper ACPI for X60.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6364
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Tue, 15 Feb 2011 00:27:24 +0000 (00:27 +0000)]
Remove Inagua Kconfig items for external VGA and AHCI binaries. These can be addded by the developer if needed.
Fixes abuild issues.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6363
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Tue, 15 Feb 2011 00:23:05 +0000 (00:23 +0000)]
SERIAL_POST was renamed to CONSOLE_POST a while ago
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6362
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Tue, 15 Feb 2011 00:14:32 +0000 (00:14 +0000)]
use git.seabios.org for checking out seabios.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6361
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Mon, 14 Feb 2011 20:02:47 +0000 (20:02 +0000)]
Lenovo ThinkPad X60 / X60s Support
Adds support for Lenovo X60 series ThinkPads. So far, only X60s
(Model 1703) has been tested.
It's a basic patch without SMI and ACPI, as this makes it easier to
review. SMI and ACPI patches will follow.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6360
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Mon, 14 Feb 2011 19:26:22 +0000 (19:26 +0000)]
Use fprintf(stderr, ...) in library
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6359
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Mon, 14 Feb 2011 19:25:27 +0000 (19:25 +0000)]
Stub out FILE*, stdout/stdin/stderr and implement fprintf on these
- Add FILE*
- Add stdout, stdin, stderr stubs
- Add fprintf that redirects to printf for stdout and stderr and fails otherwise
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6358
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Mon, 14 Feb 2011 19:24:37 +0000 (19:24 +0000)]
lpgcc was too noisy in some cases
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6357
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Mon, 14 Feb 2011 19:23:33 +0000 (19:23 +0000)]
Some more POSIX compatibility
- Add assert.h
- Add arpa/inet.h
- Add assert macro
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6356
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Josef Kellermann [Mon, 14 Feb 2011 19:21:28 +0000 (19:21 +0000)]
Errata #169 works on HT, not MC
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6355
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Mon, 14 Feb 2011 19:19:58 +0000 (19:19 +0000)]
Removed LPC DMA Deadlock workaround...
Setting bit#21 in k8_f0#68 is part of the errata#169
which is handled in amdk8/coherent.c
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6354
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Mon, 14 Feb 2011 19:15:36 +0000 (19:15 +0000)]
Fix Typo. (and why is that file, and some of its siblings per-board?)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6353
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Frank Vibrans [Mon, 14 Feb 2011 19:04:45 +0000 (19:04 +0000)]
Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8.
This code provides support for IBASE Technology DB-FT1 (AMD code name Persimmon) and AMD Inagua platforms. It is dependent on all other patches in this set.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6352
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 19:00:13 +0000 (19:00 +0000)]
This code provides support for the superio chip on the AMD Inagua platform (not commercially available). It is independent of the AMD>code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6351
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 18:56:10 +0000 (18:56 +0000)]
I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6350
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Frank Vibrans [Mon, 14 Feb 2011 18:52:15 +0000 (18:52 +0000)]
This code provides support for the superio chip on the IBASE Technology DB-FT1 (AMD code name Persimmon) platform. It is independent of the AMD code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6349
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 18:47:37 +0000 (18:47 +0000)]
This code fixes a number of build issues related to the AMD Agesa code. The particular issues are global variables existing in romstage and the use of GCC intrinsics in the build. The former issue will be addressed shortly, and the latter issue requires community assistance. This code is dependent on the AMD Family 14h mainboard code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6348
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 18:42:12 +0000 (18:42 +0000)]
Add AMD cpu wrapper code. Patch 4 of 8.
This code provides cpu early initialization for Family 14h cpus. It is dependent on the AMD Agesa code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6347
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Frank Vibrans [Mon, 14 Feb 2011 18:38:14 +0000 (18:38 +0000)]
This code provides southbridge initialization for SB800 south bridges. It is dependent on the AMD CIMx/SB800 code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6346
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Frank Vibrans [Mon, 14 Feb 2011 18:35:15 +0000 (18:35 +0000)]
This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6345
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Frank Vibrans [Mon, 14 Feb 2011 18:30:54 +0000 (18:30 +0000)]
Add AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.
This code currently generates many warnings that are functionally benign. These are being addressed, but the wheels of bureaucracy turn slowly. This drop supports AMD cpu families 10h and 14h. Only Family 14h is used as an example in this set of patches. Other cpu families are supported by the infrastructure, but their specific support is not included herein. This patch is functionally independent of the other patches in this set.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6344
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Rudolf Marek [Sat, 12 Feb 2011 16:24:48 +0000 (16:24 +0000)]
Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early only Serial/SIO/RTC.
Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6343
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1