Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6343
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
/* DMA enable */
pci_write_config8(dev, 0x40, 0x04);
-
- /* IO Port Decode Enable */
- pci_write_config8(dev, 0x44, 0xFF);
- pci_write_config8(dev, 0x45, 0xFF);
- pci_write_config8(dev, 0x46, 0xC3);
- pci_write_config8(dev, 0x47, 0xFF);
-
- // TODO: This has already been done(?)
- /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
- * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
- * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65). */
- byte = pci_read_config8(dev, 0x48);
- byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */
- byte |= 1 << 6; /* enable for RTC I/O range */
- pci_write_config8(dev, 0x48, byte);
+ /* LPC Sync Timeout */
pci_write_config8(dev, 0x49, 0xFF);
- /* Enable 0x480-0x4bf, 0x4700-0x470B */
- byte = pci_read_config8(dev, 0x4A);
- byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
- pci_write_config8(dev, 0x4A, byte);
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
pci_write_config8(dev, 0x7C, 0x05);
struct bus *link;
u32 reg, reg_x;
int var_num = 0;
- u16 reg_var[3];
+ u16 reg_var[3] = {0x0, 0x0, 0x0};
+ u8 wiosize = pci_read_config8(dev, 0x74);
reg = pci_read_config32(dev, 0x44);
reg_x = pci_read_config32(dev, 0x48);
case 0x2f8: /* COM2 */
reg |= (1 << 7);
break;
- case 0x378: /* Parallal 1 */
+ case 0x378: /* Parallel 1 */
reg |= (1 << 0);
+ reg |= (1 << 1); /* + 0x778 for ECP */
break;
case 0x3f0: /* FD0 */
reg |= (1 << 26);
break;
- case 0x220: /* Aduio 0 */
+ case 0x220: /* Audio 0 */
reg |= (1 << 8);
break;
case 0x300: /* Midi 0 */
switch (var_num) {
case 0:
reg_x |= (1 << 2);
+ if ((end - base) < 16)
+ wiosize |= (1 << 0);
break;
case 1:
reg_x |= (1 << 24);
+ if ((end - base) < 16)
+ wiosize |= (1 << 2);
break;
case 2:
reg_x |= (1 << 25);
+ reg_x |= (1 << 24);
+ if ((end - base) < 16)
+ wiosize |= (1 << 3);
break;
}
reg_var[var_num++] =
pci_write_config16(dev, 0x64, reg_var[0]);
break;
}
+ pci_write_config8(dev, 0x74, wiosize);
}
static void sb600_lpc_enable_resources(device_t dev)
/* DMA enable */
pci_write_config8(dev, 0x40, 0x04);
- /* IO Port Decode Enable */
- pci_write_config8(dev, 0x44, 0xFF);
- pci_write_config8(dev, 0x45, 0xFF);
- pci_write_config8(dev, 0x46, 0xC3);
- pci_write_config8(dev, 0x47, 0xFF);
-
- /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
- * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
- * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65).
- * Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/
- byte = pci_read_config8(dev, 0x48);
- byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */
- byte |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
- byte |= 1 << 6; /* enable for RTC I/O range */
- pci_write_config8(dev, 0x48, byte);
+ /* LPC Sync Timeout */
pci_write_config8(dev, 0x49, 0xFF);
- /* Enable 0x480-0x4bf, 0x4700-0x470B */
- byte = pci_read_config8(dev, 0x4A);
- byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
- pci_write_config8(dev, 0x4A, byte);
/* Set LPC ROM size, it has been done in sb800_lpc_init().
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
struct bus *link;
u32 reg, reg_x;
int var_num = 0;
- u16 reg_var[3];
+ u16 reg_var[3] = {0x0, 0x0, 0x0};
+ u8 wiosize = pci_read_config8(dev, 0x74);
reg = pci_read_config32(dev, 0x44);
reg_x = pci_read_config32(dev, 0x48);
case 0x2f8: /* COM2 */
reg |= (1 << 7);
break;
- case 0x378: /* Parallal 1 */
+ case 0x378: /* Parallel 1 */
reg |= (1 << 0);
+ reg |= (1 << 1); /* + 0x778 for ECP */
break;
case 0x3f0: /* FD0 */
reg |= (1 << 26);
break;
- case 0x220: /* Aduio 0 */
+ case 0x220: /* Audio 0 */
reg |= (1 << 8);
break;
case 0x300: /* Midi 0 */
switch (var_num) {
case 0:
reg_x |= (1 << 2);
+ if ((end - base) < 16)
+ wiosize |= (1 << 0);
break;
case 1:
reg_x |= (1 << 24);
+ if ((end - base) < 16)
+ wiosize |= (1 << 2);
break;
case 2:
reg_x |= (1 << 25);
+ reg_x |= (1 << 24);
+ if ((end - base) < 16)
+ wiosize |= (1 << 3);
break;
}
reg_var[var_num++] =
pci_write_config16(dev, 0x64, reg_var[0]);
break;
}
+ pci_write_config8(dev, 0x74, wiosize);
}
static void sb800_lpc_enable_resources(device_t dev)
projects / coreboot.git / commitdiff