endif
endif
+
+config UPDATE_CPU_MICROCODE
+ bool
+ default y
+
+config UPDATE_CPU_MICROCODE
+ bool "Update CPU microcode"
+ default y
+ depends on EXPERT && CPU_AMD_MODEL_10XXX
+ help
+ Select this to apply patches to the CPU microcode provided by
+ AMD without source, and distributed with coreboot, to address
+ issues in the CPU post production.
+
+ Microcode updates distributed with coreboot are not necessarily
+ the latest version available from AMD. Updates are only applied
+ if they are newer than the microcode already in your CPU.
+
+ Unselect this to let Fam10h CPUs run with microcode as shipped
+ from factory. No binary microcode patches will be included in the
+ coreboot image in that case, which can help with creating an image
+ for which complete source code is available, which in turn might
+ simplify license compliance.
+
+ Microcode updates intend to solve issues that have been discovered
+ after CPU production. The common case is that systems work as
+ intended with updated microcode, but we have also seen cases where
+ issues were solved by not applying the microcode updates.
+
+ Note that some operating system include these same microcode
+ patches, so you may need to also disable microcode updates in
+ your operating system in order for this option to matter.
-# no conditionals here. If you include this file from a socket, then you get all the binaries.
driver-y += model_10xxx_init.c
-ramstage-y += update_microcode.c
+ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c
ramstage-y += apic_timer.c
ramstage-y += processor_name.c
* This happens after HTinit.
* The BSP runs this code in it's own path.
*/
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(cpuid_eax(1));
+#endif
cpuSetAMDMSR();
#if CONFIG_SET_FIDVID
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/early_setup.c"
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();