Improving BKDG implementation of P-states,

CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index 18e2a0762f6f472aa005368358936719515f077c..e1ee71a5a7968358777768679839a5b0d3b55e59 100644 (file)
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -394,19 +394,6 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
        } else {        /* SVI */
                /* set slamVidMode to 1 for SVI */
                dword |= VID_SLAM_ON;
-
-               u32 dtemp = dword;
-
-               /* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd]  */
-               dword = pci_read_config32(dev, 0xD8);
-
-               if (dtemp & DUAL_VDD_BIT)
-                       dword |= PWR_PLN_ON;
-               else
-                       dword &= PWR_PLN_OFF;
-               pci_write_config32(dev, 0xD8, dword);
-
-                dword = dtemp;
         }
         /* set the rest of A0 since we're at it... */