Following patch fills in the callbacks for PCIe x16 resets. This board uses GPM8...

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
index 09ace66fcaee40906ea2503936a7ece037be21fe..c7eedeafb81b8805a6c745fce862a56d7a600c82 100644 (file)
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ b/src/mainboard/asrock/939a785gmh/mainboard.c
@@ -35,12 +35,31 @@ uint64_t uma_memory_base, uma_memory_size;
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);
+
+static void pcie_rst_toggle(u8 val) {
+       u8 byte;
+
+       byte = pm_ioread(0x8d);
+       byte &= ~(3 << 1);
+       pm_iowrite(0x8d, byte);
+
+       byte = pm_ioread(0x94);
+       /* Output enable */
+       byte &= ~(3 << 2);
+       /* Toggle GPM8, GPM9 */
+       byte &= ~(3 << 0);
+       byte |= val;
+       pm_iowrite(0x94, byte);
+}
+
 void set_pcie_dereset()
 {
+    pcie_rst_toggle(0x3);
 }
 
 void set_pcie_reset()
 {
+    pcie_rst_toggle(0x0);
 }
 
 #if 0       /* not tested yet */