libpayload: Add more libpci-compatibility (#defines)

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/payloads/libpayload/include/pci.h b/payloads/libpayload/include/pci.h
index 2490f6cb4cc2aba38c57e316898afb422b0b823c..005634a75048c4412720393cf9023d962a0afa15 100644 (file)
--- a/payloads/libpayload/include/pci.h
+++ b/payloads/libpayload/include/pci.h
@@ -42,6 +42,8 @@ typedef u32 pcidev_t;
 #define REG_SUBSYS_VENDOR_ID 0x2C
 #define REG_SUBSYS_ID   0x2E
 
+#define REG_COMMAND_IO  (1 << 0)
+#define REG_COMMAND_MEM (1 << 1)
 #define REG_COMMAND_BM  (1 << 2)
 
 #define HEADER_TYPE_NORMAL  0

diff --git a/payloads/libpayload/include/pci/pci.h b/payloads/libpayload/include/pci/pci.h
index 9c7ced8621bcfa5244185ae23da172e403075024..53da0e17560250fd59682c14433917ec967fea20 100644 (file)
--- a/payloads/libpayload/include/pci/pci.h
+++ b/payloads/libpayload/include/pci/pci.h
@@ -39,6 +39,32 @@
 #define PCI_SUBSYSTEM_VENDOR_ID REG_SUBSYS_VENDOR_ID\r
 #define PCI_SUBSYSTEM_ID       REG_SUBSYS_ID\r
 \r
+#define PCI_COMMAND            REG_COMMAND\r
+#define PCI_COMMAND_IO         REG_COMMAND_IO\r
+#define PCI_COMMAND_MEMORY     REG_COMMAND_MEM\r
+#define PCI_COMMAND_MASTER     REG_COMMAND_BM\r
+\r
+#define PCI_HEADER_TYPE                REG_HEADER_TYPE\r
+#define PCI_HEADER_TYPE_NORMAL HEADER_TYPE_NORMAL\r
+#define PCI_HEADER_TYPE_BRIDGE HEADER_TYPE_BRIDGE\r
+#define PCI_HEADER_TYPE_CARDBUS        HEADER_TYPE_CARDBUS\r
+\r
+#define PCI_BASE_ADDRESS_0     0x10\r
+#define PCI_BASE_ADDRESS_1     0x14\r
+#define PCI_BASE_ADDRESS_2     0x18\r
+#define PCI_BASE_ADDRESS_3     0x1c\r
+#define PCI_BASE_ADDRESS_4     0x20\r
+#define PCI_BASE_ADDRESS_5     0x24\r
+#define PCI_BASE_ADDRESS_SPACE 1 // mask\r
+#define PCI_BASE_ADDRESS_SPACE_IO      1\r
+#define PCI_BASE_ADDRESS_SPACE_MEM     0\r
+#define PCI_BASE_ADDRESS_IO_MASK       ~0xf\r
+#define PCI_BASE_ADDRESS_MEM_MASK      ~0x3\r
+\r
+#define PCI_ROM_ADDRESS                0x30\r
+#define PCI_ROM_ADDRESS1       0x38 // on bridges\r
+#define PCI_ROM_ADDRESS_MASK   ~0x7ff\r
+\r
 struct pci_dev {\r
        u16 domain;\r
        u8 bus, dev, func;\r