Sven Schnelle [Wed, 2 Feb 2011 23:49:41 +0000 (23:49 +0000)]
Add detection/dump support for the NSC PC87382.
It is a rather small 'Super I/O' device, containing a serial port, IR,
GPIO, and a Docking LPC switch. It is used in various Thinkpads.
Add 0x164e/0x16ef to the list of probed ports for NSC chips, as
Thinkpads are using this address pair.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6327
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Sven Schnelle [Tue, 1 Feb 2011 19:19:53 +0000 (19:19 +0000)]
Properly add Lenovo EC to build
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6326
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Sven Schnelle [Tue, 1 Feb 2011 10:44:26 +0000 (10:44 +0000)]
Add support for the Lenovo PMH7 embedded controller
Lenovo PMH7 (Power Management Hardware Hub) is found in
most recent (starting with X60/T60 AFAIK) Lenovo/IBM Laptops.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6325
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Mathias Krause [Tue, 1 Feb 2011 10:42:52 +0000 (10:42 +0000)]
Fix using custom build configs in abuild
The undocumented config argument for the -t option implicitly assumes
the config file is within the mainboard directory but fails to honor
this assumption when it comes to copying the file.
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6324
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Stefan Reinauer [Mon, 31 Jan 2011 21:16:48 +0000 (21:16 +0000)]
Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if
a rare condition arises.
Based on findings by Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6323
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Alexandru Gagniuc [Mon, 31 Jan 2011 21:14:02 +0000 (21:14 +0000)]
Add PCI ID's for VIA K8T800 and K8M800 northbridges.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6322
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Stefan Reinauer [Mon, 31 Jan 2011 21:03:14 +0000 (21:03 +0000)]
Build failure because of src/pc80/mc146818rtc_early.c unused variable
Fixes #173
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Stefan Reinauer <reinauer@google.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6321
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Patrick Georgi [Sun, 30 Jan 2011 16:37:39 +0000 (16:37 +0000)]
Replace special rules for auxiliary files by cbfs-files-y entries
VGABIOS, Intel MBI and the bootsplash image were added with special
build rules. These are replaced by generic cbfs-files-y entries now.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6320
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Patrick Georgi [Sun, 30 Jan 2011 16:31:15 +0000 (16:31 +0000)]
Inverse two arguments of cbfs-files-y and adapts its users (one of which already used the new order)
This is in reponse to feedback that the original setup was too complicated.
New cbfs-files-y behaviour:
cbfs-files-y contains the names of files as they appear in CBFS. The
arguments describe the on-filesystem name, the type and (optionally) the
position. Example:
cbfs-files-y += foo
foo-file := bar
foo-type := splashscreen
foo-position := 0xffff8000
This configures a CBFS file called "foo" that is marked "splashscreen",
located at 0xffff8000 in flash and contains the data of the file "bar"
in the filesystem (either in the current directory, ie. where the
corresponding Makefile.inc resides, or if that doesn't exist, relative
to the toplevel directory).
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6319
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Kevin O'Connor [Sun, 30 Jan 2011 07:40:32 +0000 (07:40 +0000)]
Make cbfstool available in $(obj) for simple user access.
- integrated Peter's suggestion ($< $@)
- removed @ prefix, we use the .SILENT pseudo-target
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6318
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Stefan Reinauer [Sat, 29 Jan 2011 05:51:54 +0000 (05:51 +0000)]
Pass all required toolchain parts to SeaBIOS correctly
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6317
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Rudolf Marek [Fri, 28 Jan 2011 20:57:48 +0000 (20:57 +0000)]
Attached patch fixes the LPC decode ranges of SB700. We enable early only Serial/SIO/RTC. Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6316
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Stefan Reinauer [Fri, 28 Jan 2011 08:05:54 +0000 (08:05 +0000)]
This patch gets usbdebug console working in romstage.
- actually hook up usbdebug in printk/print_ for romstage
- make usbdebug.c more similar to the Linux kernel version it was
originally derived from.
- increase retries and timing for usbdebug init (at least one chipset
seems to need this)
- src/pc80/usbdebug_serial.c is not needed
- some small console cleanups
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6315
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Patrick Georgi [Fri, 28 Jan 2011 07:56:39 +0000 (07:56 +0000)]
Separate CMOS layout from lbtable handling
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6314
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Patrick Georgi [Fri, 28 Jan 2011 07:54:11 +0000 (07:54 +0000)]
Move CMOS handling into separate files in accessors
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6313
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Patrick Georgi [Fri, 28 Jan 2011 07:50:33 +0000 (07:50 +0000)]
Move the parser for cmos.layout text files to accessors
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6312
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Stefan Reinauer [Fri, 28 Jan 2011 07:47:35 +0000 (07:47 +0000)]
rename CONFIG_SERIAL_POST to CONFIG_CONSOLE_POST
because that is what it does.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6311
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Patrick Georgi [Fri, 28 Jan 2011 07:47:10 +0000 (07:47 +0000)]
Move CLI portion of nvramtool into cli/ subdirectory as first step towards librarization.
Also: update one regex wrapper user.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6310
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Patrick Georgi [Fri, 28 Jan 2011 07:41:10 +0000 (07:41 +0000)]
Eliminate a couple of 3-line functions that barely wrap *printf calls
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6309
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Patrick Georgi [Fri, 28 Jan 2011 07:40:08 +0000 (07:40 +0000)]
No need to add varargs magic to a simple regex wrapper.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6308
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Stefan Reinauer [Fri, 28 Jan 2011 01:06:39 +0000 (01:06 +0000)]
Fix Bimini build
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6307
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Stefan Reinauer [Fri, 28 Jan 2011 01:03:18 +0000 (01:03 +0000)]
rk886ex lacked EC_ACPI
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6306
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Stefan Reinauer [Thu, 27 Jan 2011 23:56:48 +0000 (23:56 +0000)]
Only add EC code if EC is selected in Kconfig
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6305
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Sven Schnelle [Thu, 27 Jan 2011 11:43:03 +0000 (11:43 +0000)]
Add new ec subdir for Embedded Controllers and common ACPI EC support
Adds a new src/ec subdir for embedded controllers (mostly found in laptops)
and converts Getac P470 and Roda RK886EX to use the new ACPI EC instead
of having their own copies of those functions.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6304
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Peter Stuge [Thu, 27 Jan 2011 11:09:36 +0000 (11:09 +0000)]
SMM code on i945 platforms needs udelay()
smm-y wasn't required before, because udelay.c used to be #included from
various files in src/mainboard.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6303
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Patrick Georgi [Thu, 27 Jan 2011 07:39:38 +0000 (07:39 +0000)]
Add a new CMOS variable which triggers activation of the
LPT port. With the CMOS variable set, LPT is found by SeaBIOS,
with the variable reset, it's not.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302
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Zheng Bao [Thu, 27 Jan 2011 03:31:50 +0000 (03:31 +0000)]
Trivial. Re-indent the code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6301
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Zheng Bao [Thu, 27 Jan 2011 02:19:55 +0000 (02:19 +0000)]
Set the phy via weak function.
As Rudolf called.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6300
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Stefan Reinauer [Thu, 27 Jan 2011 01:11:20 +0000 (01:11 +0000)]
oops. this is weird. CAR addresses should be specified in the socket and not in
the board. I thought we did this ages ago.
Also push CAR BASE further down so it won't conflict with a 32mbit flash part.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299
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Stefan Reinauer [Tue, 25 Jan 2011 19:27:23 +0000 (19:27 +0000)]
Fix abuild
thanks to Kevin who came up with this
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6298
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Zheng Bao [Tue, 25 Jan 2011 06:06:58 +0000 (06:06 +0000)]
Set the SB800 SATA PHY correctly.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6297
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Stefan Reinauer [Mon, 24 Jan 2011 21:27:22 +0000 (21:27 +0000)]
If the tool has 64bit issues, we need to find and fix them. No papering over them.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6296
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Josef Kellermann [Mon, 24 Jan 2011 21:07:57 +0000 (21:07 +0000)]
This patch fixes an 'write_tables: coreboot table didn't fit (f0221)' issue.
Signed-off-by: Josef Kellermann <Joseph.Kellermann@heitec.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6295
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Rudolf Marek [Mon, 24 Jan 2011 21:05:53 +0000 (21:05 +0000)]
Add CFLAGS when compiling resulting executable. It broke 64bit systems, because the rest uses -m32 now.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6294
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Zheng Bao [Mon, 24 Jan 2011 07:50:07 +0000 (07:50 +0000)]
Change fadt revision back to 3.
The AcpiPmaCntBlk have to be set.
Further research is needed to find out why.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6293
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Kevin O'Connor [Sun, 23 Jan 2011 06:47:09 +0000 (06:47 +0000)]
Clone a tag rather than SeaBIOS stable branch HEAD
Use a tag (rel-0.6.1.3) for SeaBIOS stable checkouts instead of the
stable branch. The tag is a little safer because it prevents an
incorrect commit to the stable branch from being immiediately picked
up by coreboot users.
Note - rel-0.6.1.3 (and 0.6.1-stable) now have the CFLAGS build fix
that was causing build failures for coreboot users.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6292
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Patrick Georgi [Fri, 21 Jan 2011 13:20:10 +0000 (13:20 +0000)]
... And fix the other compile time issues in cmos_layout.bin support
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6291
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Patrick Georgi [Fri, 21 Jan 2011 12:45:37 +0000 (12:45 +0000)]
Make YABEL warnings-are-errors safe
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6290
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Patrick Georgi [Fri, 21 Jan 2011 11:43:06 +0000 (11:43 +0000)]
Typo. s,CMOS_COMPONENT,CBFS_COMPONENT,.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6289
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Zheng Bao [Fri, 21 Jan 2011 08:46:27 +0000 (08:46 +0000)]
Now bimini can boot linux to login.
Note:
1. bimini_fam10/Kconfig: Set GENERATE_MP_TABLE in Kconfig. This will make sure the
smp_write_config_table will run. Then intr_data will be written
into 0xC00/0xC01.
2. bootblock: Use PCI_DEV(0, 0x14, 3) instead of
pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_LPC), 0).
The pci_locate_device will cause the system crash.
3. fadt.c: Change fadt revision to 1. 3 will cause the linux hang. Why?
4. early_setup.c: pmio 0x65 has change its meaning.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6288
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Stefan Reinauer [Fri, 21 Jan 2011 07:46:32 +0000 (07:46 +0000)]
push ts5300 rom size to 1MB. In fact the flash part on that
board is 2MB and the entry point is somewhere in the middle. quite weird setup
http://www.embeddedarm.com/products/board-detail.php?product=TS-5300
We should probably wipe the board from the tree. It will not work anyways with
current coreboot and the architecture is kind of obscure.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6287
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Patrick Georgi [Fri, 21 Jan 2011 07:29:40 +0000 (07:29 +0000)]
Add nvramtool -D option that allows taking cmos data from
a plain binary file. Overrides using cmos.default in CBFS
if both -C and -D are given.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6286
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Patrick Georgi [Fri, 21 Jan 2011 07:24:08 +0000 (07:24 +0000)]
Add nvramtool -C option that takes a CBFS file as argument.
When using this option, nvramtool looks for a cmos_layout.bin
and cmos.default in the image and uses these for layout information
and CMOS data.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6285
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Patrick Georgi [Fri, 21 Jan 2011 07:19:59 +0000 (07:19 +0000)]
Add support for working on in-memory CMOS data (eg.
as loaded from a file).
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6284
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Patrick Georgi [Fri, 21 Jan 2011 07:18:20 +0000 (07:18 +0000)]
Abstract CMOS accesses a bit more in preparation of using
files for CMOS data.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6283
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Patrick Georgi [Fri, 21 Jan 2011 07:04:05 +0000 (07:04 +0000)]
There's another place where nvramtool can look for
the CMOS checksum specification.
When using nvramtool on files (instead of CMOS and runtime firmware)
it's the only place.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6282
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Thu, 20 Jan 2011 06:28:25 +0000 (06:28 +0000)]
Remove the code for debugging.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6281
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 20 Jan 2011 05:59:22 +0000 (05:59 +0000)]
S3 feanture of SB800. Compiliant with SB700.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6280
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 20 Jan 2011 05:41:11 +0000 (05:41 +0000)]
Move some board specific functions to sb800.h.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6279
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 20 Jan 2011 05:29:37 +0000 (05:29 +0000)]
Features of Bimini board:
RS785
SB800
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6278
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 20 Jan 2011 04:45:48 +0000 (04:45 +0000)]
This sb800 code is derived from sb700.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6277
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 20 Jan 2011 02:09:24 +0000 (02:09 +0000)]
For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the freq limit in
mcti_d.c:
static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
{
pDCTstat->PresetmaxFreq = 800;
}
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6276
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Wed, 19 Jan 2011 07:25:26 +0000 (07:25 +0000)]
Add a GX2 Kconfig option to choose the framebuffer size.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6275
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Wed, 19 Jan 2011 06:56:33 +0000 (06:56 +0000)]
Add Geode GX2 memmory descriptors.
Add a simple README file.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6274
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 19 Jan 2011 06:54:42 +0000 (06:54 +0000)]
Revert r5902 to make code more readable again. At least three people like to
have this go away again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Wed, 19 Jan 2011 06:32:35 +0000 (06:32 +0000)]
Now that the VIA code is run above 1Meg (like other boards), it should
cache that range instead of the first 1Meg. This reduces boot time by
about 1 second on epia-cn.
This patch also adds a MTRRphysMaskValid bit definition.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Wed, 19 Jan 2011 06:31:24 +0000 (06:31 +0000)]
The cn700.c code references mainboard_interrupt_handlers() which isn't
defined if VGA_ROM_RUN is off. Define a dummy implementation of that
function for this case.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6271
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 18 Jan 2011 14:38:59 +0000 (14:38 +0000)]
Fix fwrite tests.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6270
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 18 Jan 2011 14:28:45 +0000 (14:28 +0000)]
Report if cmos_layout.bin can't be found when it should.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6269
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 18 Jan 2011 13:56:36 +0000 (13:56 +0000)]
Move option table (cmos.layout's binary representation)
to CBFS and adapt coreboot to use it.
Comments by Stefan and Mathias taken into account (except for
the build time failure if the table is missing when it should
exist and the "memory leak" in build_opt_tbl)
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6268
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 18 Jan 2011 12:14:08 +0000 (12:14 +0000)]
Remove overengineering, part 1/many
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6267
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 18 Jan 2011 12:12:47 +0000 (12:12 +0000)]
Eliminate strict aliasing related warnings.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6266
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Tue, 18 Jan 2011 09:36:44 +0000 (09:36 +0000)]
remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6265
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Tue, 18 Jan 2011 09:34:31 +0000 (09:34 +0000)]
remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6264
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Tue, 18 Jan 2011 09:32:15 +0000 (09:32 +0000)]
remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6263
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Tue, 18 Jan 2011 09:31:29 +0000 (09:31 +0000)]
remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6262
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Tue, 18 Jan 2011 09:29:19 +0000 (09:29 +0000)]
remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6261
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Mon, 17 Jan 2011 05:08:32 +0000 (05:08 +0000)]
cbfstool: When extracting, refer to files in CBFS as file instead of payload
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6260
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Mon, 17 Jan 2011 05:02:09 +0000 (05:02 +0000)]
cbfstool: Trivial move of newline after commands in usage
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6259
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Mon, 17 Jan 2011 02:20:33 +0000 (02:20 +0000)]
The code is tested on my board with register DIMMs. More tests need to be
done. Please send the testing report.
Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set
to a higher limit, otherwise the frequnce will be set as 400MHz.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6258
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Sun, 16 Jan 2011 17:15:36 +0000 (17:15 +0000)]
Ooops lets see if this extra comment removal fixes this.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6257
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Sun, 16 Jan 2011 16:23:51 +0000 (16:23 +0000)]
Trivial, cleanup of GPIO comments.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6256
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 14 Jan 2011 08:36:34 +0000 (08:36 +0000)]
Disable CMOS recovery code for ROMCC boards as the CBFS code used for
that feature is not ROMCC compatible.
Fixes build errors introduced in r6253.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6255
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 14 Jan 2011 07:41:42 +0000 (07:41 +0000)]
Improved GPIO setup for roda/rk886ex, and some documentation
on what the GPIOs are used for.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6254
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 14 Jan 2011 07:40:24 +0000 (07:40 +0000)]
Allow coreboot to initialize CMOS if checksum is invalid.
If a file "cmos.default", type "cmos default"(0xaa) is in CBFS,
a wrong checksum leads to coreboot rewriting the first 128 bytes
(except for clock data) with the data in cmos.default, then
reboots the system so every component of coreboot works with the
same set of values.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6253
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 13 Jan 2011 11:40:38 +0000 (11:40 +0000)]
Default to CRT on Kontron/986lcd-m. "default display" doesn't always
select the right output device.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6252
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 13 Jan 2011 11:38:46 +0000 (11:38 +0000)]
Improve compatibility of YABEL with real-world VGABIOSes
Some of them do weird things to the option rom region (mapping
registers there or so) which failed as we handled these memory
region in emulation. As they were copied back to real memory
after the emulation was done, we can just as well use real
memory directly for these regions.
This affects IVT, BDA, and option ROM space.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6251
2b7e53f0-3cfb-0310-b3e9-
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Aurelien Guillaume [Thu, 13 Jan 2011 09:09:21 +0000 (09:09 +0000)]
Add "cbfstool extract" function.
It dumps everything you ask for, but you might not
get what you expect if the file is compressed or
otherwise converted (eg. payloads in SELF format).
(Originally it would only extract "raw" files.
This is a change by me, as filetypes are commonly used
to differentiate raw data files --Patrick)
Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6250
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 12 Jan 2011 21:09:25 +0000 (21:09 +0000)]
drop unused files
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6249
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Tue, 11 Jan 2011 02:15:57 +0000 (02:15 +0000)]
change a readable way to fix SB800 CIMX "multi-character constant warning".
by using 'Int32FromChar' macro, instead of the ASCII code.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6248
2b7e53f0-3cfb-0310-b3e9-
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Marc Bertens [Thu, 6 Jan 2011 23:03:46 +0000 (23:03 +0000)]
Various Nokia IP530 fixes.
- Correct default ROM image size for this board (512KB is correct).
- devicetree.cb: Add AUX I/O config (mainly GPIO settings).
This allows you to control the LEDs in the front panel and JP900/JP901
can be read.
- irq_tables.c: Rework PIRQ table to make more onboard devices work.
Also, avoid IRQ9.
- mainboard.c: Drop unneeded functions, everything is done in devicetree.cb.
Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6247
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 6 Jan 2011 02:18:12 +0000 (02:18 +0000)]
Fix some settings fo AMD MCT. It is based on BIOS test suite.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 5 Jan 2011 02:40:53 +0000 (02:40 +0000)]
uart_init is only used in romstage.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6245
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 5 Jan 2011 02:27:53 +0000 (02:27 +0000)]
move single options out of main menu and remove stray "options"
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6244
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 5 Jan 2011 02:10:50 +0000 (02:10 +0000)]
fix compilation of mconf on some systems.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6243
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 5 Jan 2011 01:37:48 +0000 (01:37 +0000)]
fix "make clean"
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6242
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Tue, 4 Jan 2011 19:51:33 +0000 (19:51 +0000)]
MCP55: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6241
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Tue, 4 Jan 2011 17:36:55 +0000 (17:36 +0000)]
CK804: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6240
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Tue, 4 Jan 2011 06:39:29 +0000 (06:39 +0000)]
Trivial:
add missed CIMx file to romstage. in order to link them into romstage, move all CIMx table to .rodata section.
Run dos2unix on Makefile.inc, which is not upstream CIMx code
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6239
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Tue, 4 Jan 2011 06:15:46 +0000 (06:15 +0000)]
Trivial: use the IO_APIC_ADDR constant defined in ioapic.h, and spell check
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6238
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 1 Jan 2011 23:36:03 +0000 (23:36 +0000)]
src/southbridge/amd/cimx_wrapper: Run dos2unix on the files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6237
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 1 Jan 2011 23:30:37 +0000 (23:30 +0000)]
AMD SB800: Drop component prefix from filenames.
We did the same with other chipsets in r6150.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6236
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 1 Jan 2011 22:05:57 +0000 (22:05 +0000)]
Add detection support for the ITE IT8721F.
Tested on hardware by me.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6235
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 1 Jan 2011 18:58:39 +0000 (18:58 +0000)]
AMD Bimini: Use mptable_init() in mptable.c.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6234
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 1 Jan 2011 18:40:02 +0000 (18:40 +0000)]
AMD Bimini: Small fixes, and updates to recent trunk conventions.
- Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed
to HAVE_DEBUG_CAR in r5898.
- Move QRANK_DIMM_SUPPORT to Kconfig, see r6028.
- Drop obsolete/unused COMPRESS, see r6145.
- Drop obsolete SET_NB_CFG_54, see r6086.
- Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077.
Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it.
- Rename some GENERATE_* options to HAVE_*, see r6027.
- Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151.
- Drop ACPI_SSDTX_NUM, the global default is 0 already.
- Random whitespace and coding style fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6233
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Uwe Hermann [Sat, 1 Jan 2011 18:10:07 +0000 (18:10 +0000)]
AMD Bimini: Drop duplicate ASL files as we did for other boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6232
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 1 Jan 2011 18:04:42 +0000 (18:04 +0000)]
Add support for the AMD Bimini eval mainboard.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6231
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 1 Jan 2011 17:52:34 +0000 (17:52 +0000)]
Add AMD SB800 southbridge support via cimx_wrapper.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6230
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 1 Jan 2011 17:44:07 +0000 (17:44 +0000)]
Add AMD SB800 southbridge CIMx code.
The main CIMx code is in a src/vendorcode directory and should not be
changed with regard to coding style etc. in order to remain easily syncable
with the "upstream" AMD code.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6229
2b7e53f0-3cfb-0310-b3e9-
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Jonathan Kollasch [Fri, 31 Dec 2010 19:20:23 +0000 (19:20 +0000)]
Use $(MAKE) instead of make when cleaning for SeaBIOS.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6228
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1