Trivial. Re-indent the code.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 505632ec765078e5fceb2f128230648f1d659707..cd5221742b95113fa2556bb2b6f46baad1036b19 100644 (file)
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -41,7 +41,8 @@ static u8 pmio_read(u8 reg)
        return inb(PM_INDEX + 1);
 }
 
-static void sb700_acpi_init(void) {
+static void sb700_acpi_init(void)
+{
        pmio_write(0x20, ACPI_PM_EVT_BLK & 0xFF);
        pmio_write(0x21, ACPI_PM_EVT_BLK >> 8);
        pmio_write(0x22, ACPI_PM1_CNT_BLK & 0xFF);
@@ -624,7 +625,8 @@ static int smbus_read_byte(u32 device, u32 address)
        return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos) {
+int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+{
        int i;
        printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 
@@ -637,7 +639,8 @@ int s3_save_nvram_early(u32 dword, int size, int  nvram_pos) {
        return nvram_pos;
 }
 
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+{
        u32 data = *old_dword;
        int i;
        for (i = 0; i<size; i++) {
@@ -653,7 +656,8 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
 }
 
 #if CONFIG_HAVE_ACPI_RESUME == 1
-static int acpi_is_wakeup_early(void) {
+static int acpi_is_wakeup_early(void)
+{
        u16 tmp;
        tmp = inw(ACPI_PM1_CNT_BLK);
        printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
@@ -661,7 +665,8 @@ static int acpi_is_wakeup_early(void) {
 }
 #endif
 
-struct cbmem_entry *get_cbmem_toc(void) {
+struct cbmem_entry *get_cbmem_toc(void)
+{
        uint32_t xdata = 0;
        int xnvram_pos = 0xfc, xi;
        for (xi = 0; xi<4; xi++) {

diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index c0732308212931148b013534f1d5428b78997fc5..a08780e521f2caec267ac8b293fd9359891ee941 100644 (file)
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -77,7 +77,8 @@ static void lpc_init(device_t dev)
 #endif
 }
 
-void set_cbmem_toc(struct cbmem_entry *toc) {
+void set_cbmem_toc(struct cbmem_entry *toc)
+{
        u32 dword = (u32) toc;
        int nvram_pos = 0xfc, i;
        for (i = 0; i<4; i++) {

diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 08b9aa8ad99d31f16287568e78308e537ecb945e..1ad9bdd9df2b42f8230a46db823254837698c592 100644 (file)
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -53,9 +53,9 @@ static int sata_drive_detect(int portnum, u16 iobar)
        return 0;
 }
 
-       /* This function can be overloaded in mainboard.c */
-
-void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev) {
+/* This function can be overloaded in mainboard.c */
+void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev)
+{
        /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
        pci_write_config16(dev, 0x86, 0x2c00);
 

diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 7ef0d8e268362ed5d58fb5fe946955da461f9545..6a7ea6c9eb9c391d47f958428bbb018a8c87b5f6 100644 (file)
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -41,7 +41,8 @@ static u8 pmio_read(u8 reg)
        return inb(PM_INDEX + 1);
 }
 
-static void sb800_acpi_init(void) {
+static void sb800_acpi_init(void)
+{
        pmio_write(0x60, ACPI_PM_EVT_BLK & 0xFF);
        pmio_write(0x61, ACPI_PM_EVT_BLK >> 8);
        pmio_write(0x62, ACPI_PM1_CNT_BLK & 0xFF);
@@ -652,7 +653,8 @@ static int smbus_read_byte(u32 device, u32 address)
        return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos) {
+int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+{
        int i;
        printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 
@@ -665,7 +667,8 @@ int s3_save_nvram_early(u32 dword, int size, int  nvram_pos) {
        return nvram_pos;
 }
 
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+{
        u32 data = *old_dword;
        int i;
        for (i = 0; i<size; i++) {
@@ -681,7 +684,8 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
 }
 
 #if CONFIG_HAVE_ACPI_RESUME == 1
-static int acpi_is_wakeup_early(void) {
+static int acpi_is_wakeup_early(void)
+{
        u16 tmp;
        tmp = inw(ACPI_PM1_CNT_BLK);
        printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
@@ -689,7 +693,8 @@ static int acpi_is_wakeup_early(void) {
 }
 #endif
 
-struct cbmem_entry *get_cbmem_toc(void) {
+struct cbmem_entry *get_cbmem_toc(void)
+{
        uint32_t xdata = 0;
        int xnvram_pos = 0xfc, xi;
        for (xi = 0; xi<4; xi++) {