Sven Schnelle [Wed, 15 Jun 2011 15:13:27 +0000 (17:13 +0200)]
Remove old ACPI code
it isn't used anywhere, and could be fetched from git/svn history if
needed.
Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/35
Tested-by: build bot (Jenkins)
Sven Schnelle [Wed, 15 Jun 2011 07:26:34 +0000 (09:26 +0200)]
i82801gx: replace
cafed00d/
cafebabe by defines
We're using '0xcafed00d' all over the code as magic for ACPI S3
resume. Let's add a define for that. Also replace 0xcafebabe by
a define.
Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/33
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Stefan Reinauer [Fri, 10 Jun 2011 18:05:53 +0000 (20:05 +0200)]
Update README with newer version of the text from the web page
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I4f181979ca5e47b27731c681a320b34cbecc0027
Reviewed-on: http://review.coreboot.org/19
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Sven Schnelle [Sun, 12 Jun 2011 14:49:13 +0000 (16:49 +0200)]
X60: handle EC events in SMM if ACPI is disabled
Change-Id: I0fee890bd2d667b54965201f5c90da3656d7af5c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/27
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sven Schnelle [Sun, 12 Jun 2011 12:35:11 +0000 (14:35 +0200)]
X60: trigger save cmos on volume/brightness change
Change-Id: I020e06bc311c4e4327c9d3cf2c379dc8fe070a7a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/25
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sven Schnelle [Mon, 6 Jun 2011 13:58:54 +0000 (15:58 +0200)]
CMOS: add set_option()
Change-Id: I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/23
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Sven Schnelle [Sun, 12 Jun 2011 13:08:58 +0000 (15:08 +0200)]
X60/T60: set CMOS defaults
Change-Id: I5789a03898cdbade67887c0389aab5c773f867d9
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/26
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Marshall Buschman [Sat, 11 Jun 2011 02:16:41 +0000 (21:16 -0500)]
ASRock/E350M1: Skip memory clear for boot time reduction
Applying Scott's patches to e350m1, svn r6600:
Memory clear is not required for non-ECC boards.
Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/20
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Sven Schnelle [Sun, 12 Jun 2011 14:55:56 +0000 (16:55 +0200)]
X60/T60: fix return value of mainboard_io_trap_handler()
The handler should return 1 if it handled the request. The current
code returns 0, which causes 'Unknown function' logs.
Change-Id: Ic296819a5f8c6f1f97b7d47148182226684882a0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/29
Tested-by: build bot (Jenkins)
Sven Schnelle [Sun, 12 Jun 2011 14:53:25 +0000 (16:53 +0200)]
log ec data with DEBUG_SPEW
Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/28
Tested-by: build bot (Jenkins)
Jonathan A. Kollasch [Wed, 8 Jun 2011 15:18:43 +0000 (10:18 -0500)]
Add ACPI automatic PIC/APIC interrupt routing logic for ck804
Change-Id: I2d462ca1220ea31af243c7a58a1dc33c39e9c840
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/13
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Uwe Hermann [Thu, 9 Jun 2011 18:56:29 +0000 (20:56 +0200)]
superiotool: Cosmetics and coding style fixes.
Change-Id: Iacda2a9e37635d5cffc5004caf588ef3e5e09b5e
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Reviewed-on: http://review.coreboot.org/18
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Sven Schnelle [Sun, 5 Jun 2011 18:47:49 +0000 (20:47 +0200)]
H8 EC: add volume CMOS setting
Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/12
Tested-by: build bot (Jenkins)
Peter Stuge [Thu, 9 Jun 2011 03:04:20 +0000 (05:04 +0200)]
util/crossgcc: Add build-without-gdb Makefile target
Change-Id: I5d02f1a23e54aa67be0cc01d921898c28c22f8e4
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/16
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
Peter Stuge [Thu, 9 Jun 2011 02:54:16 +0000 (04:54 +0200)]
util/crossgcc: Add buildgcc -G and --skip-gdb options
Change-Id: Ic31130774ad56abf0b5498b04b4890348352a621
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/15
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
Peter Stuge [Thu, 9 Jun 2011 03:06:25 +0000 (05:06 +0200)]
Change make crossgcc to build without gdb by default
Using gdb with coreboot is not (yet) very common, so at least for
now it makes sense to not build gdb by default. A make crosstools
target is also added, which runs the full build in util/crossgcc
and thus generates a toolchain with both compiler and debugger.
Change-Id: I939ebcd06ae9a1bc485fd18e70cac98112d3bbbf
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/17
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
Marc Jones [Wed, 8 Jun 2011 20:41:52 +0000 (14:41 -0600)]
Revert changes to set the sb800 to AHCI mode.
Seabios doesn't have this support included yet,
which causes the generic Persimmon and other CIMx
sb800 platforms to not boot.
Change-Id: If07328b7c62d7fc314647adce8fab983ed327854
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/14
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Cristian Măgherușan-Stanciu [Tue, 7 Jun 2011 12:55:40 +0000 (14:55 +0200)]
Add basic .gitignore
Ignore directories created by abuild, jenkins, payloads and crossgcc.
Change-Id: I7d4145fc1e54a10ffdc4b884d8b8f0ae53e615c6
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/10
Tested-by: build bot (Jenkins)
Sven Schnelle [Sun, 5 Jun 2011 19:32:51 +0000 (21:32 +0200)]
T60/PMH7: move 'touchpad' option to pmh7
This option is PMH7 specific, and should be moved there,
so all Notebook utilizing a PMH7 have this option.
For Thinkpads without Touchpad (like the X60), simply
don't add 'touchpad' to cmos.layout.
Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/6
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sven Schnelle [Sun, 5 Jun 2011 09:39:12 +0000 (11:39 +0200)]
i82801gx: enable ACPI during S3 resume
disabling ACPI during S3 wakeup breaks ACPI wakeup, as the
Host OS is assuming that ACPI is enabled.
Change-Id: I8ced72c4b553d41a57f26d64998118e8a77621f8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/7
Tested-by: build bot (Jenkins)
Sven Schnelle [Sun, 5 Jun 2011 09:33:41 +0000 (11:33 +0200)]
SMM: add defines for APM_CNT register
in the current code, the defines for the APM_CNT (0xb2) register
are duplicated in almost every place where it is used. define those
values in cpu/x86/smm.h, and only include this file.
And while at it, fixup whitespace.
Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/4
Tested-by: build bot (Jenkins)
Patrick Georgi [Sun, 5 Jun 2011 13:15:49 +0000 (15:15 +0200)]
Add "gitconfig" make target to simplify gerrit configuration
"make gitconfig" installs the gerrit commit-msg hook and validates
that user.name and user.email are configured.
No data will be overwritten.
Change-Id: I49ec98538574866e7ad6238ff3d02b9c1beef1bb
Reviewed-on: http://review.coreboot.org/2
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Sven Schnelle [Sun, 5 Jun 2011 18:43:04 +0000 (20:43 +0200)]
T60: fix touchpad option
Code used 'int' as return type, but the cmos option is only one
bit. get_option returned with the value in bit 0-7, but all remaining
bits were left unitialized by get_option(). fix this by using char
as type.
Change-Id: I60e609164277380f936f66c99ef9508fa6a6b67c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/5
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Stefan Reinauer [Sat, 4 Jun 2011 17:36:21 +0000 (10:36 -0700)]
re-indent, so files conform to coding guidelines.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab
Reviewed-on: http://review.coreboot.org/8
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Sven Schnelle [Sat, 4 Jun 2011 17:35:22 +0000 (19:35 +0200)]
SMM: add mainboard_apm_cnt() callback
motherboards can use this hook to get notified if someone writes
to the APM_CNT port (0xb2). If the hook returns 1, the chipset
specific hook is also skipped.
Change-Id: I05f1a27cebf9d25db8064f2adfd2a0f5759e48b5
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/3
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Patrick Georgi [Fri, 3 Jun 2011 19:56:13 +0000 (21:56 +0200)]
Teach abuild to emit JUnit formatted build reports
Jenkins can produce reports from JUnit test cases, so we fake testcases
for each board.
Change-Id: I34d46d15c83f4f04d2228f302eb626b261ac098d
Reviewed-on: http://review.coreboot.org/1
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Stefan Reinauer [Sat, 4 Jun 2011 16:30:27 +0000 (16:30 +0000)]
WARNINGS_ARE_ERRORS is y per default, don't set it twice.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6637
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:48:14 +0000 (15:48 +0000)]
Port persimmon r6594 to e350m1: Cosmetic cleanup
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6636
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:47:56 +0000 (15:47 +0000)]
Port persimmon r6593 to e350m1: Remove unused Kconfig options
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6635
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:47:30 +0000 (15:47 +0000)]
Port persimmon r6592 to e350m1: Update GPP port configuration
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6634
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:47:05 +0000 (15:47 +0000)]
Port persimmon r6591 to e350m1: ROM cache early
Enable rom cache early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:46:50 +0000 (15:46 +0000)]
Port persimmon r6590 to e350m1: Work around memory allocation problem
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6632
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:46:32 +0000 (15:46 +0000)]
Port persimmon r6589 to e350m1: Strip down AGESA options
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6631
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:46:13 +0000 (15:46 +0000)]
Port persimmon r6588 to e350m1: VGA framebuffer
Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6630
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:45:46 +0000 (15:45 +0000)]
Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6629
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:45:29 +0000 (15:45 +0000)]
Port persimmon r6586 to e350m1: FADT revision
Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6628
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:45:12 +0000 (15:45 +0000)]
Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:44:54 +0000 (15:44 +0000)]
Port persimmon r6583 to e350m1: pstate 0 early
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:44:31 +0000 (15:44 +0000)]
Port persimmon r6582 to e350m1: 33 MHz SPI read early
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6625
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:44:14 +0000 (15:44 +0000)]
Port persimmon r6578 and r6596 to e350m1: MMCONF base
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6624
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:43:56 +0000 (15:43 +0000)]
Port persimmon r6574 to e350m1: MMCONF size
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6623
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:43:38 +0000 (15:43 +0000)]
Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from
dfffffff to
fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6622
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:43:15 +0000 (15:43 +0000)]
Port persimmon r6572 to e350m1: I/O APIC ID
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6621
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:40:12 +0000 (15:40 +0000)]
vt8237r: Simplify bootblock init to work around nested if() romcc problem
During the hackathon in Prague we discovered that romcc has a problem
compiling the previous nested if() statements correctly. This patch
makes the code a little simpler, and indeed works around the romcc issue.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6620
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marc Jones [Fri, 3 Jun 2011 19:59:52 +0000 (19:59 +0000)]
This patch sets max freq defaults for ddr2 and ddr3for fam10.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Alexandru Gagniuc [Fri, 3 Jun 2011 19:46:25 +0000 (19:46 +0000)]
Correct wrong PCI ID for VIA K8M890 Chrome.
With the K8T800/M800 patch from r6367 the PCI IDs for the VIA chrome were
moved to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly.
(3220 instead of 3230). This patch defines the correct PCI ID for this device.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6618
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Fri, 3 Jun 2011 10:14:56 +0000 (10:14 +0000)]
advansus/a785e-i mainboard enable warning as error
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6617
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Wed, 1 Jun 2011 19:54:16 +0000 (19:54 +0000)]
Really fix iasl filename issues in our build system
There's a remaining issue that iasl cuts of "\..*$" from
output paths, even if that substring contains "/" (ie.
across directories)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6616
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Wed, 1 Jun 2011 19:29:48 +0000 (19:29 +0000)]
Report build result from abuild (did all requested boards build?)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6615
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Wed, 1 Jun 2011 02:00:30 +0000 (02:00 +0000)]
trivial remove blanks at the end of line
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6614
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Wed, 1 Jun 2011 01:56:49 +0000 (01:56 +0000)]
This patch fix a AMD sb800 wrapper compile warning:
src/southbridge/amd/cimx_wrapper/sb800/late
call clear_ioapic but not include the prototype declare header file.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Mon, 23 May 2011 22:48:13 +0000 (22:48 +0000)]
We don't have pausing versions of single-IO instructions.
Hence remove the wrong comment.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6612
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Mon, 23 May 2011 22:43:43 +0000 (22:43 +0000)]
AP_IN_SIPI_WAIT is already defined in the CPU Kconfig of those boards.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6611
2b7e53f0-3cfb-0310-b3e9-
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Jonathan Kollasch [Mon, 23 May 2011 17:55:20 +0000 (17:55 +0000)]
Correct implementation of r6608.
(.align actually takes its argument in bytes)
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6610
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Mon, 23 May 2011 17:16:44 +0000 (17:16 +0000)]
exclude src/vendorcode from GPLv2 license checks.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6609
2b7e53f0-3cfb-0310-b3e9-
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Jonathan Kollasch [Sun, 22 May 2011 15:39:25 +0000 (15:39 +0000)]
Ensure ck804 romstrap is 16-byte aligned.
This alignment seems to be necessary for the chip to recognize it.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6608
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Sat, 21 May 2011 22:18:59 +0000 (22:18 +0000)]
Add regression test for build directory handling to make lint target
A couple of scenarios that were fixed in the last few revisions are
tested to ensure that it's easy to determine breakage.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6607
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 20 May 2011 23:31:41 +0000 (23:31 +0000)]
Handle absolute source file paths
We used to fail there because we unconditionally prefixed the relative directory where it was referenced.
Tested in various scenarios:
- obj=build
- obj=../obj
- obj=$PWD/../obj
- obj=/some/other/absolute/path
- obj=/./some/other/absolute/path
In-tree relative paths still work as before, the only change in behaviour is when a source file name (as specified in one of the *-y variables) starts with "/".
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6606
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 20 May 2011 23:08:12 +0000 (23:08 +0000)]
Handle both cases, obj being absolute and relative
gnu make's handling of filenames is less than optimal. It simply
compares strings, so foo/../bar is different from bar, even though
they're logically the same.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6605
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 20 May 2011 22:17:58 +0000 (22:17 +0000)]
Fix building with relative path to object directory outside the source tree
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6604
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 20 May 2011 22:16:49 +0000 (22:16 +0000)]
iasl still can't cope with extra "." in file paths
It's really a work around, but given how this issue seems to come
back again and again, let's work around it.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6603
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 20 May 2011 22:14:07 +0000 (22:14 +0000)]
Fix ccache behaviour if more than one ccache in PATH
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6602
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Fri, 20 May 2011 17:50:14 +0000 (17:50 +0000)]
Correct amd persimmon romstage code for early SPI prefetch enable.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Fri, 20 May 2011 00:06:09 +0000 (00:06 +0000)]
Move the ACPI FACP table to the front of the RSDT list. This is done to work around a Windows XP or Server 2003 setup failure where an error message such as: "An unexpected error (
805262864) occurred at line 1768 of d:\xpclient\base\boot\setup\arcdisp.c" occurs. This change updates AMD reference board projects, but could applied to others as well.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6600
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Mon, 16 May 2011 15:32:28 +0000 (15:32 +0000)]
Move crossgcc rules to coreboot specific Makefile
Toplevel Makefile should (as far as possible) be coreboot-agnostic,
we have Makefile.inc for that.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6599
2b7e53f0-3cfb-0310-b3e9-
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Cristian Magherusan-Stanciu [Mon, 16 May 2011 01:35:03 +0000 (01:35 +0000)]
Add crossgcc target to automatically build reference toolchain
This means that a simple:
$ make crossgcc
creates the reference toolchain in the correct directory. Thanks to the
dependency on the clean-for-update target, an existing .xcompile along
with any compiled objects in build/ will be cleaned out, so the next
build will automatically use the newly created reference toolchain.
Signed-off-by: Cristian Magherusan-Stanciu <cristi.magherusan@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6598
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Mon, 16 May 2011 00:05:50 +0000 (00:05 +0000)]
cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6597
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Sun, 15 May 2011 23:13:54 +0000 (23:13 +0000)]
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6596
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Sun, 15 May 2011 22:40:40 +0000 (22:40 +0000)]
agesa_wrapper: Avoid repetitive Kconfig depends, trivial
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6595
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:10:15 +0000 (22:10 +0000)]
Cosmetic cleanup.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:09:09 +0000 (22:09 +0000)]
1) Remove unused kconfig options.
2) Correct UMA graphics PCI device ID.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:07:56 +0000 (22:07 +0000)]
Update gpp port configuration.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:06:09 +0000 (22:06 +0000)]
Enable rom cache early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6591
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:05:00 +0000 (22:05 +0000)]
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6590
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:03:45 +0000 (22:03 +0000)]
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6589
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:02:27 +0000 (22:02 +0000)]
Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6588
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:00:23 +0000 (22:00 +0000)]
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6587
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:59:19 +0000 (21:59 +0000)]
Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6586
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:56:03 +0000 (21:56 +0000)]
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6585
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:54:04 +0000 (21:54 +0000)]
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:51:31 +0000 (21:51 +0000)]
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6583
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:48:22 +0000 (21:48 +0000)]
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:45:46 +0000 (21:45 +0000)]
Build device paths for AP cores so that coreboot will report them to the OS.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6581
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:41:00 +0000 (21:41 +0000)]
Program the I/O APIC ID.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6580
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:38:08 +0000 (21:38 +0000)]
Enable AHCI mode and hide IDE controller to reduce boot time.
Note: enable AHCI in seabios and apply seabios patch:
http://www.mail-archive.com/seabios@seabios.org/msg00437.html
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6579
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:26:04 +0000 (21:26 +0000)]
Move mmconf base from
e0000000 to
f8000000 to avoid conflict with UMA BAR.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:19:54 +0000 (21:19 +0000)]
Fix ACPI shutdown function by removing reliance on SMI.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6577
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:18:59 +0000 (21:18 +0000)]
Configure CIMx to use 33 MHz fast mode for SPD read.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6576
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:13:00 +0000 (21:13 +0000)]
Match DIMM SPD addressing to implemented slots.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6575
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:11:41 +0000 (21:11 +0000)]
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6574
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:10:20 +0000 (21:10 +0000)]
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from
dfffffff to
fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6573
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:07:43 +0000 (21:07 +0000)]
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6572
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:06:30 +0000 (21:06 +0000)]
Correct the number of MCA error reporting banks cleared.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6571
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:01:42 +0000 (21:01 +0000)]
1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.
2) Remove coreboot variable MTRR initialization because AMD reference code handles it.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6570
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Fri, 13 May 2011 06:25:16 +0000 (06:25 +0000)]
siemens/sitemp_g1p1: Adapt read_option() to latest changes
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6569
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 12 May 2011 06:53:52 +0000 (06:53 +0000)]
Remove uart_init() in Siemens sitemp-g1p1
uart_init() was moved to common code in r6531, but I
missed that when integrating the new mainboard code.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6568
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Wed, 11 May 2011 07:47:43 +0000 (07:47 +0000)]
Add Siemens SITEMP-G1 board
The code is loosely based on AMD dbm690t (and copied from there)
and adapted to match the Siemens SITEMP-G1 board.
It boots both Linux and Windows XP (and if it doesn't then complain
with me [Patrick] because in that case I must have messed it up when
integrating the patch)
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6567
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Wed, 11 May 2011 07:44:27 +0000 (07:44 +0000)]
Work around unclean CMOS handling for now
Stefan switched away from #ifdef across the tree (and is absolutely right with that), but
unfortunately there are some special cases that trigger in even more special situations.
Revert one such change selectively. It's destined to go once CMOS is reworked.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6566
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 10 May 2011 21:53:13 +0000 (21:53 +0000)]
Change read_option() to a macro that wraps some API uglyness
Simplify
read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
to
read_option(foo, somedefault)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Vikram Narayanan [Tue, 10 May 2011 21:47:57 +0000 (21:47 +0000)]
This replaces the fixed shift values in the apic timer init with macros.
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6564
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1