projects / coreboot.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 2cc5f55) | patch
Enable SPI cacheline prefetch early to reduce boot time.
authorScott Duplichan <scott@notabs.org>
Sun, 15 May 2011 21:56:03 +0000 (21:56 +0000)
committerMarc Jones <marc.jones@amd.com>
Sun, 15 May 2011 21:56:03 +0000 (21:56 +0000)
commitb7e068305c4186608ae70a6af8a3862a43a68b8d
tree177e1486539ee9dcc6ae4e169d25541a68f2f0bdtree | snapshot
parent2cc5f550c72ac6a13da798b8f073e3d5c55177e0commit | diff
Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/mainboard/amd/persimmon/romstage.c diff | blob | history
my coreboot WIP stuff (asus m5a99x-evo board)