Correct amd persimmon romstage code for early SPI prefetch enable.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 1bcb0d14077b330b34d6d9b45e193dda58ed678a..3f2aa1032917469d8bc24eedd466a2791b27f6dd 100644 (file)
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -74,7 +74,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
   if (boot_cpu())
     {
     __outdword (0xcf8, 0x8000a3b8);
-    __outdword (0xcfc, __indword (0xcfc) | 0 << 24);
+    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
     }
 
   // early enable of SPI 33 MHz fast mode read