This patch sets max freq defaults for ddr2 and ddr3for fam10.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h
index e93c0c7dc999f4b712ed72f080fe8062645acafb..2f92c15d0ebdfc8ed8b00ec700493562fae264cc 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mct.h
+++ b/src/northbridge/amd/amdmct/mct/mct.h
@@ -496,18 +496,6 @@ struct DCTStatStruc {              /* A per Node structure*/
                                           0=disable
                                           1=enable*/
 
-#ifndef MAX_NODES_SUPPORTED
-#define MAX_NODES_SUPPORTED    8
-#endif
-
-#ifndef MAX_DIMMS_SUPPORTED
-#define MAX_DIMMS_SUPPORTED    8
-#endif
-
-#ifndef MAX_CS_SUPPORTED
-#define MAX_CS_SUPPORTED       8
-#endif
-
 
 /* global function */
 u32 NodePresent(u32 Node);

diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
index 2976c8225bd88213db456ce45e9492db472cb17a..058e056e42e36834a4c34d33f0e3a41bd79c1c39 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d.h
@@ -667,23 +667,6 @@ struct DCTStatStruc {              /* A per Node structure*/
                                        yy1b = enable with DctSelIntLvAddr set to yyb */
 
 
-#ifndef MAX_NODES_SUPPORTED
-#define MAX_NODES_SUPPORTED    8
-#endif
-
-#ifndef MAX_DIMMS_SUPPORTED
-#define MAX_DIMMS_SUPPORTED    8
-#endif
-
-#ifndef MAX_CS_SUPPORTED
-#define MAX_CS_SUPPORTED       8
-#endif
-
-#ifndef MCT_DIMM_SPARE_NO_WARM
-#define MCT_DIMM_SPARE_NO_WARM 0
-#endif
-
-
 u32 Get_NB32(u32 dev, u32 reg);
 void Set_NB32(u32 dev, u32 reg, u32 val);
 u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 0894b3f88d8be0cca2875cae9f3379ec53bc9d55..119153623490ee4007e3358ecdf602dd4931ce3a 100644 (file)
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -1315,7 +1315,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
        u16 word;
 
        /* Get CPU Si Revision defined limit (NPT) */
-       proposedFreq = 533;      /* Rev F0 programmable max memclock is */
+       proposedFreq = 800;      /* Rev F0 programmable max memclock is */
 
        /*Get User defined limit if  "limit" mode */
        if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index a7b6697b756746f2c7dea52b5ad75dadf5fa818c..69a495c27a2128f71d0bcbbb351a680c4ee01a94 100644 (file)
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -728,22 +728,6 @@ struct DCTStatStruc {              /* A per Node structure*/
                                        yy1b = enable with DctSelIntLvAddr set to yyb */
 
 
-#ifndef MAX_NODES_SUPPORTED
-#define MAX_NODES_SUPPORTED    8
-#endif
-
-#ifndef MAX_DIMMS_SUPPORTED
-#define MAX_DIMMS_SUPPORTED    8
-#endif
-
-#ifndef MAX_CS_SUPPORTED
-#define MAX_CS_SUPPORTED       8
-#endif
-
-#ifndef MCT_DIMM_SPARE_NO_WARM
-#define MCT_DIMM_SPARE_NO_WARM 0
-#endif
-
 u32 Get_NB32(u32 dev, u32 reg);
 void Set_NB32(u32 dev, u32 reg, u32 val);
 u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);

diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h
index 357f2cb9bcd73cae94ea910e5bdc9761f32252fd..9c948fe2a188a667a74e641a4c7103bf9c53580b 100644 (file)
--- a/src/northbridge/amd/amdmct/wrappers/mcti.h
+++ b/src/northbridge/amd/amdmct/wrappers/mcti.h
@@ -57,6 +57,18 @@ UPDATE AS NEEDED
 #define MAX_CS_SUPPORTED               8
 #endif
 
+#ifndef MCT_DIMM_SPARE_NO_WARM
+#define MCT_DIMM_SPARE_NO_WARM 0
+#endif
+
+#ifndef MEM_MAX_LOAD_FREQ
+#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+ #define MEM_MAX_LOAD_FREQ             800
+#else
+ #define MEM_MAX_LOAD_FREQ             400
+#endif
+#endif
+
 #define MCT_TRNG_KEEPOUT_START         0x00000C00
 #define MCT_TRNG_KEEPOUT_END           0x00000CFF
 

diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 569d61c7b03ba572770fc0cebdfc1d4fd1100944..4af75fd0e203a08dcc3761062aa254ed2d5eba21 100644 (file)
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -48,7 +48,7 @@ static u16 mctGet_NVbits(u8 index)
                //val =  200;   /* 200MHz(DDR400) */
                //val =  266;   /* 266MHz(DDR533) */
                //val =  333;   /* 333MHz(DDR667) */
-               val =  400;     /* 400MHz(DDR800) */
+               val =  MEM_MAX_LOAD_FREQ;;      /* 400MHz(DDR800) */
                break;
        case NV_ECC_CAP:
 #if SYSTEM_TYPE == SERVER
@@ -237,7 +237,7 @@ static void mctHookAfterDIMMpre(void)
 
 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 {
-       pDCTstat->PresetmaxFreq = 400;
+       pDCTstat->PresetmaxFreq = MEM_MAX_LOAD_FREQ;
 }
 
 #ifdef UNUSED_CODE