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(parent: d9a634c) | patch
Enable SPI cacheline prefetch early to reduce boot time.
authorScott Duplichan <scott@notabs.org>
Sun, 15 May 2011 21:54:04 +0000 (21:54 +0000)
committerMarc Jones <marc.jones@amd.com>
Sun, 15 May 2011 21:54:04 +0000 (21:54 +0000)
commit2cc5f550c72ac6a13da798b8f073e3d5c55177e0
tree3e024874a10cd2f84f3d78554b6a6aa856ef0295tree | snapshot
parentd9a634c7560d0af50e141ad18ffc8c48519209e7commit | diff
Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/mainboard/amd/persimmon/romstage.c diff | blob | history
my coreboot WIP stuff (asus m5a99x-evo board)