#define X86_VENDOR_SIS 10
#define X86_VENDOR_UNKNOWN 0xff
-#if !defined( __ROMCC__ ) && defined( __GNUC__)
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) && defined( __GNUC__)
#include <device/device.h>
#ifndef ARCH_HLT_H
#define ARCH_HLT_H
-#if defined( __ROMCC__) && !defined(__GNUC__)
+#if defined( __ROMCC__) && !defined(__PRE_RAM__) && !defined(__GNUC__)
static void hlt(void)
{
__builtin_hlt();
* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
* versions of the single-IO instructions (inb_p/inw_p/..).
*/
-#if defined( __ROMCC__ ) && !defined (__GNUC__)
+#if defined( __ROMCC__ ) && !defined (__GNUC__)
static inline void outb(uint8_t value, uint16_t port)
{
__builtin_outb(value, port);
* set in some auto.c files to trigger the simple device_t version to be used.
* So __GNUCC__ does the right thing here.
*/
-#if defined (__GNUCC__)
+#if defined (__ROMCC__)
#define STATIC
#else
#define STATIC static
#include <arch/cpu.h>
#include <cpu/amd/dualcore.h>
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
#include <cpu/amd/model_fxx_msr.h>
#endif
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
#include <stdint.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
/* NOTE: We use the APIC TIMER register is to hold flags for AP init during
- * pre-memory init (ROMCC). Don't use init_timer() and udelay is redirected
- * to udelay_tsc().
+ * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is
+ * redirected to udelay_tsc().
*/
*/
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
/* From the Revision Guide :
* Equivalent Processor Table for AMD Family 10h Processors
#include <arch/cpu.h>
#include <cpu/amd/quadcore.h>
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
#include <cpu/amd/model_10xxx_msr.h>
#endif
#include <arch/asm.h>
// Make sure no stage 2 code is included:
-#define __ROMCC__
+#define __PRE_RAM__
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?
+++ /dev/null
-subdirs-y += onboard
+++ /dev/null
-config chip.h
-
-object onboard.o
-
+++ /dev/null
-obj-y += onboard.o
+++ /dev/null
-#ifndef PCI_ONBOARD_H
-#define PCI_ONBOARD_H
-
-struct drivers_pci_onboard_config
-{
- unsigned long rom_address;
-};
-struct chip_operations;
-extern struct chip_operations drivers_pci_onboard_ops;
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004 Tyan Computer
- * by yhlu@tyan.com
- */
-
-#include <console/console.h>
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "chip.h"
-
-/*
- * How to use the onboard device driver for option rom execution:
- *
- * 1. You need to add the driver to your mainboard Config.lb:
- *
- * chip drivers/pci/onboard
- * device pci x.0 on end
- * register "rom_address" = "0xfff80000"
- * end
- * 2. Reduce the size of your normal (or fallback) image, by adding the
- * following lines to your target Config.lb, after romimage "normal"
- * # 48K for SCSI FW or ATI ROM
- * option CONFIG_ROM_SIZE = 512*1024-48*1024
- * 3. Create your vgabios.bin, for example using awardeco and put it in the
- * directory of your target Config.lb. You can also read an option rom from
- * a running system, but this is unreliable, as some option roms are changed
- * during execution:
- * # dd if=/dev/mem of=atix.rom skip=1536 count=96
- * 4. After you built coreboot.rom, attach the option rom to your coreboot
- * image:
- * # cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom
- *
- * Alternatively you can use the following script "nsxv" to build your image
- * Usage:
- * # ./nsxv s2850
- *
- * #!/bin/bash
- * MBVENDOR=tyan
- * MBMODEL=$1
- * LBROOT=/home/yhlu/xx/xx
- *
- * echo $1
- * date
- *
- * cd "$LBROOT/freebios2/targets"
- * rm -rf "$MBVENDOR/$MBMODEL/$MBMODEL"
- * ./buildtarget "$MBVENDOR/$MBMODEL" &> "$LBROOT/x_b.txt"
- * cd "$MBVENDOR/$MBMODEL/$MBMODEL"
- * #make clean
- * eval make &> "$LBROOT/x_m.txt"
- * if [ $? -eq 0 ]; then
- * echo "ok."
- * else
- * echo "FAILED! Log excerpt:"
- * tail -n 15 "$LBROOT/x_m.txt"
- * exit
- * fi
- * cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom"
- * cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/
- *
- * date
- *
- */
-
-static void onboard_enable(device_t dev)
-{
- struct drivers_pci_onboard_config *conf;
- conf = dev->chip_info;
- dev->rom_address = conf->rom_address;
-}
-
-struct chip_operations drivers_pci_onboard_ops = {
- CHIP_NAME("Onboard PCI")
- .enable_dev = onboard_enable,
-};
// ROMCC doesn't support __FILE__ or __LINE__ :^{
#if CONFIG_DEBUG
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
#define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); }
#else
#define ASSERT(x) { \
#define ASSERT(x) { }
#endif
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
#define BUG() { die("BUG encountered: system halted\r\n"); }
#else
#define BUG() { \
struct node_core_id get_node_core_id(unsigned int nb_cfg_54);
#endif
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
struct device;
unsigned get_apicid_base(unsigned ioapic_num);
void amd_sibling_init(struct device *cpu);
}
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
static int is_e0_later_in_bsp(int nodeid)
{
uint32_t val;
return (cpuid_eax(1) & 0xfff0f) < 0x40f02;
}
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
//AMD_F0_SUPPORT
static int is_cpu_f0_in_bsp(int nodeid)
{
#define TOP_MEM_MASK 0x007fffff
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
-#if !defined( __ROMCC__ ) && !defined (ASSEMBLY)
+#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) && !defined(__PRE_RAM__)
void amd_setup_mtrrs(void);
#endif /* __ROMCC__ */
struct node_core_id get_node_core_id(u32 nb_cfg_54);
#endif
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
struct device;
u32 get_apicid_base(u32 ioapic_num);
void amd_sibling_init(struct device *cpu);
wbinvd();
}
-#if !defined( __ROMCC__) && defined (__GNUC__)
+#if !defined( __ROMCC__) && !defined(__PRE_RAM__) && defined (__GNUC__)
void x86_enable_cache(void);
#endif /* !__ROMCC__ */
}
#endif
-#if ! defined (__ROMCC__)
+#if ! defined (__ROMCC__) && !defined(__PRE_RAM__)
#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
#endif /* CONFIG_SMP */
-#endif /* !__ROMCC__ */
+#endif /* !__ROMCC__ && !__PRE_RAM__ */
#endif /* CPU_X86_LAPIC_H */
#ifndef CPU_X86_MSR_H
#define CPU_X86_MSR_H
-#if defined( __ROMCC__) && !defined (__GNUC__)
+#if defined( __ROMCC__)
typedef __builtin_msr_t msr_t;
);
}
-#endif /* ROMCC__ && !__GNUC__ */
+#endif /* __ROMCC__ */
#endif /* CPU_X86_MSR_H */
#define MTRRfix4K_F8000_MSR 0x26f
-#if !defined(__ROMCC__) && !defined (ASSEMBLY)
+#if !defined(__ROMCC__) && !defined (ASSEMBLY) && !defined(__PRE_RAM__)
#include <device/device.h>
return res;
}
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined (__PRE_RAM__)
static inline unsigned long long rdtscll(void)
{
unsigned long long val;
#define MIN(a,b) ((a) < (b) ? (a) : (b))
#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
void *malloc(size_t size);
void free(void *ptr);
#endif
void *memmove(void *dest, const void *src, size_t n);
void *memset(void *s, int c, size_t n);
int memcmp(const void *s1, const void *s2, size_t n);
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
int sprintf(char * buf, const char *fmt, ...);
#endif
return 0;
}
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
static inline char *strdup(const char *s)
{
size_t sz = strlen(s) + 1;
u64 size;
} __attribute__((packed));
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
struct cbmem_entry *bss_cbmem_toc;
#endif
struct cbmem_entry *cbmem_toc;
cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
bss_cbmem_toc = cbmem_toc;
#endif
cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
debug("Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr);
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
bss_cbmem_toc = cbmem_toc;
#endif
{
struct cbmem_entry *cbmem_toc;
int i;
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
#else
cbmem_toc = bss_cbmem_toc;
{
struct cbmem_entry *cbmem_toc;
int i;
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
#else
cbmem_toc = bss_cbmem_toc;
return (void *)NULL;
}
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
#if CONFIG_HAVE_ACPI_RESUME
extern u8 acpi_slp_type;
#endif
cbmem_arch_init();
}
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
void cbmem_list(void)
{
struct cbmem_entry *cbmem_toc;
int i;
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
#else
cbmem_toc = bss_cbmem_toc;
/*
* 2006.12.10 yhlu moved it to corbeoot and use struct instead
*/
-#ifndef __ROMCC__
+#if !defined(__ROMCC__)
#include <console/console.h>
#else
#if CONFIG_USE_PRINTK_IN_CAR==0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define SYSTEM_TYPE 0 /* SERVER */
//#define SYSTEM_TYPE 1 /* DESKTOP */
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <device/pci_def.h>
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
/* Used by it8712f_enable_serial(). */
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define QRANK_DIMM_SUPPORT 1
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/pci.h>
#define PCI_ID(VENDOR_ID, DEVICE_ID) \
((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-// __ROMCC__ means: use "unsigned" for device, not a struct.
-#define __ROMCC__
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
#include <cbmem.h>
// Now, this needs to be included because it relies on the symbol
-// __ROMCC_ being set during CAR stage (in order to compile the
+// __PRE_RAM__ being set during CAR stage (in order to compile the
// BSS free versions of the functions). Either rewrite the code
// to be always BSS free, or invent a flag that's better suited than
-// __ROMCC__ to determine whether we're in ram init stage (stage 1)
+// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
//
#include "lib/cbmem.c"
* MA 02110-1301 USA
*/
-#define __ROMCC__
+#define __PRE_RAM__
#include <delay.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#define ASSEMBLY 1
+#define __PRE_RAM__
#include <stdint.h>
#include <device/pci_def.h>
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
* MA 02110-1301 USA
*/
-// __ROMCC__ means: use "unsigned" for device, not a struct.
-#define __ROMCC__
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
#include <cbmem.h>
// Now, this needs to be included because it relies on the symbol
-// __ROMCC_ being set during CAR stage (in order to compile the
+// __PRE_RAM__ being set during CAR stage (in order to compile the
// BSS free versions of the functions). Either rewrite the code
// to be always BSS free, or invent a flag that's better suited than
-// __ROMCC__ to determine whether we're in ram init stage (stage 1)
+// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
//
#include "lib/cbmem.c"
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
// #define DEBUG_SMBUS 1
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
* Additional (C) 2007 coresystems GmbH
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define K8_ALLOCATE_IO_RANGE 1
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define QRANK_DIMM_SUPPORT 1
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
//used by raminit
#define QRANK_DIMM_SUPPORT 1
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define QRANK_DIMM_SUPPORT 1
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define K8_ALLOCATE_IO_RANGE 1
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#include "amdfam10_nums.h"
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
#if NODE_NUMS==64
#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#else
#if CONFIG_AMDMCT == 0
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
static void soft_reset(void);
#endif
static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
#else
printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
}
}
if(needs_reset) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
print_debug("mem trained failed\n");
soft_reset();
#else
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
typedef struct sys_info sys_info_conf_t;
#else
typedef struct amdfam10_sysconf_t sys_info_conf_t;
{
device_t dev;
struct dram_base_mask_t d;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
#else
dev = __f1_dev[0];
#endif
for(i=0;i<nodes;i++) {
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
#endif
}
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = NODE_PCI(nodeid, 1);
#else
dev = __f1_dev[nodeid];
static void set_DctSelBaseAddr(u32 i, u32 sel_m)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
static u32 get_DctSelBaseAddr(u32 i)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
static void set_DctSelHiEn(u32 i, u32 val)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
static u32 get_DctSelHiEn(u32 i)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
static void set_DctSelBaseOffset(u32 i, u32 sel_off_m)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
static u32 get_DctSelBaseOffset(u32 i)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
d = get_dram_base_mask(i);
d.mask += (carry_over>>9);
set_dram_base_mask(i,d, nodes);
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = NODE_PCI(nodeid, 1);
#else
dev = __f1_dev[nodeid];
#endif
tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24);
for(i=0; i<nodes; i++) {
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
if(ht_c_index<4) {
#endif
for(i=0; i<nodes; i++) {
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
}
#endif
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
u32 io_min, u32 io_max, u32 nodes)
{
/* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
for(i=0; i<nodes; i++) {
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
}
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
for(i=0; i<nodes; i++){
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
#endif
/* io range allocation */
for(i=0; i<nodes; i++) {
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
for(ht_c_index=1;ht_c_index<4; ht_c_index++) {
u32 i;
for(i=0; i<nodes; i++) {
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
u32 dword;
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
dev = NODE_PCI(node, 0);
#else
dev = __f0_dev[node];
#endif
}
-#if !defined(__ROMCC__)
+#if !defined(__PRE_RAM__)
static u32 get_io_addr_index(u32 nodeid, u32 linkn)
{
u32 index;
uint32_t sbbusn;
} __attribute__((packed));
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
static void soft_reset(void);
#else
void hard_reset(void);
}
for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n");
#else
printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
}
}
if(needs_reset) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
print_debug("mem trained failed\r\n");
soft_reset();
#else
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
static void cn700_noop()
{
}
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H
#define SOUTHBRIDGE_AMD_CS5530_CS5530_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
void cs5530_enable(device_t dev);
#endif
#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
void i82371eb_enable(device_t dev);
void i82371eb_hard_reset(void);
#ifndef I82801CA_H
#define I82801CA_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801ca_enable(device_t dev);
#endif
/* __ROMCC__ is set by auto.c to make sure
* none of the stage2 data structures are included.
*/
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801gx_enable(device_t dev);
#endif
#ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
#define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801xx_enable(device_t dev);
#endif
projects / coreboot.git / commitdiff