6 #include <device/pci_def.h>
8 #include <device/pnp_def.h>
9 #include <arch/romcc_io.h>
10 #include <cpu/x86/lapic.h>
11 #include "option_table.h"
12 #include "pc80/mc146818rtc_early.c"
13 #include "pc80/serial.c"
14 #include "arch/i386/lib/console.c"
15 #include "lib/ramtest.c"
17 #include <cpu/amd/model_fxx_rev.h>
18 #include "northbridge/amd/amdk8/incoherent_ht.c"
19 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
20 #include "northbridge/amd/amdk8/raminit.h"
21 #include "cpu/amd/model_fxx/apic_timer.c"
22 #include "lib/delay.c"
24 #include "cpu/x86/lapic/boot_cpu.c"
25 #include "northbridge/amd/amdk8/reset_test.c"
26 #include "northbridge/amd/amdk8/debug.c"
27 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
29 #include "cpu/amd/mtrr/amd_earlymtrr.c"
30 #include "cpu/x86/bist.h"
32 #include "northbridge/amd/amdk8/setup_resource_map.c"
34 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
37 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
39 static void memreset_setup(void)
41 if (is_cpu_pre_c0()) {
42 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
45 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
47 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
50 static void memreset(int controllers, const struct mem_controller *ctrl)
52 if (is_cpu_pre_c0()) {
54 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
58 static inline void activate_spd_rom(const struct mem_controller *ctrl)
60 #define SMBUS_HUB 0x18
62 unsigned device=(ctrl->channel0[0])>>8;
63 /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
66 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
67 } while ((ret!=0) && (i-->0));
69 smbus_write_byte(SMBUS_HUB, 0x03, 0);
72 static inline void change_i2c_mux(unsigned device)
74 #define SMBUS_HUB 0x18
76 print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
79 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
80 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
81 } while ((ret!=0) && (i-->0));
82 ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
83 print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
87 static inline int spd_read_byte(unsigned device, unsigned address)
89 return smbus_read_byte(device, address);
92 #define QRANK_DIMM_SUPPORT 1
94 #include "northbridge/amd/amdk8/raminit.c"
95 #include "northbridge/amd/amdk8/coherent_ht.c"
96 #include "lib/generic_sdram.c"
98 /* tyan does not want the default */
99 #include "resourcemap.c"
101 #if CONFIG_LOGICAL_CPUS==1
102 #define SET_NB_CFG_54 1
104 #include "cpu/amd/dualcore/dualcore.c"
106 #define RC0 ((1<<2)<<8)
107 #define RC1 ((1<<1)<<8)
108 #define RC2 ((1<<4)<<8)
109 #define RC3 ((1<<3)<<8)
116 #include "cpu/amd/car/copy_and_run.c"
118 #include "cpu/amd/car/post_cache_as_ram.c"
120 #include "cpu/amd/model_fxx/init_cpus.c"
122 #if CONFIG_USE_FALLBACK_IMAGE == 1
124 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
125 #include "northbridge/amd/amdk8/early_ht.c"
127 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
129 unsigned last_boot_normal_x = last_boot_normal();
131 /* Is this a cpu only reset? or Is this a secondary cpu? */
132 if ((cpu_init_detectedx) || (!boot_cpu())) {
133 if (last_boot_normal_x) {
140 /* Nothing special needs to be done to find bus 0 */
141 /* Allow the HT devices to be found */
143 enumerate_ht_chain();
145 amd8111_enable_rom();
147 /* Is this a deliberate reset by the bios */
148 if (bios_reset_detected() && last_boot_normal_x) {
151 /* This is the primary cpu how should I boot? */
152 else if (do_normal_boot()) {
159 __asm__ volatile ("jmp __normal_image"
161 : "a" (bist), "b" ( cpu_init_detectedx ) /* inputs */
169 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
171 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
174 #if CONFIG_USE_FALLBACK_IMAGE == 1
175 failover_process(bist, cpu_init_detectedx);
177 real_main(bist, cpu_init_detectedx);
181 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
183 static const uint16_t spd_addr [] = {
184 RC0|DIMM0, RC0|DIMM2, 0, 0,
185 RC0|DIMM1, RC0|DIMM3, 0, 0,
186 #if CONFIG_MAX_PHYSICAL_CPUS > 1
187 RC1|DIMM0, RC1|DIMM2, 0, 0,
188 RC1|DIMM1, RC1|DIMM3, 0, 0,
190 #if CONFIG_MAX_PHYSICAL_CPUS > 2
191 RC2|DIMM0, RC2|DIMM2, 0, 0,
192 RC2|DIMM1, RC2|DIMM3, 0, 0,
193 RC3|DIMM0, RC3|DIMM2, 0, 0,
194 RC3|DIMM1, RC3|DIMM3, 0, 0,
199 unsigned bsp_apicid = 0;
201 struct mem_controller ctrl[8];
205 bsp_apicid = init_cpus(cpu_init_detectedx);
209 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
213 /* Halt if there was a built in self test failure */
214 report_bist_failure(bist);
216 setup_s4882_resource_map();
218 needs_reset = setup_coherent_ht_domain();
220 wait_all_core0_started();
221 #if CONFIG_LOGICAL_CPUS==1
222 // It is said that we should start core1 after all core0 launched
224 wait_all_other_cores_started(bsp_apicid);
227 // automatically set that for you, but you might meet tight space
228 needs_reset |= ht_setup_chains_x();
231 print_info("ht reset -\r\n");
235 allow_all_aps_stop(bsp_apicid);
238 //It's the time to set ctrl now;
239 fill_mem_ctrl(nodes, ctrl, spd_addr);
244 sdram_initialize(nodes, ctrl);