src/mainboard/tyan/s2880/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #include <stdint.h>
   5 #include <string.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include <stdlib.h>
  12 #include "option_table.h"
  13 #include "pc80/mc146818rtc_early.c"
  14 #include "pc80/serial.c"
  15 #include "arch/i386/lib/console.c"
  16 #include "lib/ramtest.c"
  17
  18
  19 #include <cpu/amd/model_fxx_rev.h>
  20 #include "northbridge/amd/amdk8/incoherent_ht.c"
  21 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  22 #include "northbridge/amd/amdk8/raminit.h"
  23 #include "cpu/amd/model_fxx/apic_timer.c"
  24 #include "lib/delay.c"
  25
  26 #include "cpu/x86/lapic/boot_cpu.c"
  27 #include "northbridge/amd/amdk8/reset_test.c"
  28 #include "northbridge/amd/amdk8/debug.c"
  29 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  30
  31 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  32 #include "cpu/x86/bist.h"
  33
  34 #include "northbridge/amd/amdk8/setup_resource_map.c"
  35
  36 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  37
  38 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  39
  40 static void memreset_setup(void)
  41 {
  42    if (is_cpu_pre_c0()) {
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  44    }
  45    else {
  46         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  47    }
  48         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  49 }
  50
  51 static void memreset(int controllers, const struct mem_controller *ctrl)
  52 {
  53    if (is_cpu_pre_c0()) {
  54         udelay(800);
  55         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  56         udelay(90);
  57    }
  58 }
  59
  60 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  61 {
  62         /* nothing to do */
  63 }
  64
  65 static inline int spd_read_byte(unsigned device, unsigned address)
  66 {
  67         return smbus_read_byte(device, address);
  68 }
  69
  70 #define QRANK_DIMM_SUPPORT 1
  71
  72 #include "northbridge/amd/amdk8/raminit.c"
  73 #include "northbridge/amd/amdk8/resourcemap.c"
  74 #include "northbridge/amd/amdk8/coherent_ht.c"
  75 #include "lib/generic_sdram.c"
  76
  77 #if CONFIG_LOGICAL_CPUS==1
  78 #define SET_NB_CFG_54 1
  79 #endif
  80 #include "cpu/amd/dualcore/dualcore.c"
  81
  82 #include "cpu/amd/car/copy_and_run.c"
  83
  84 #include "cpu/amd/car/post_cache_as_ram.c"
  85
  86 #include "cpu/amd/model_fxx/init_cpus.c"
  87
  88
  89 #if CONFIG_USE_FALLBACK_IMAGE == 1
  90
  91 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  92 #include "northbridge/amd/amdk8/early_ht.c"
  93
  94 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
  95 {
  96         unsigned last_boot_normal_x = last_boot_normal();
  97
  98         /* Is this a cpu only reset? or Is this a secondary cpu? */
  99         if ((cpu_init_detectedx) || (!boot_cpu())) {
 100                 if (last_boot_normal_x) {
 101                         goto normal_image;
 102                 } else {
 103                         goto fallback_image;
 104                 }
 105         }
 106
 107         /* Nothing special needs to be done to find bus 0 */
 108         /* Allow the HT devices to be found */
 109
 110         enumerate_ht_chain();
 111
 112         amd8111_enable_rom();
 113
 114         /* Is this a deliberate reset by the bios */
 115         if (bios_reset_detected() && last_boot_normal_x) {
 116                 goto normal_image;
 117         }
 118         /* This is the primary cpu how should I boot? */
 119         else if (do_normal_boot()) {
 120                 goto normal_image;
 121         }
 122         else {
 123                 goto fallback_image;
 124         }
 125  normal_image:
 126         __asm__ volatile ("jmp __normal_image"
 127                 : /* outputs */
 128                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 129                 );
 130
 131  fallback_image:
 132         ;
 133 }
 134 #endif
 135
 136 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 137
 138 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 139 {
 140
 141 #if CONFIG_USE_FALLBACK_IMAGE == 1
 142         failover_process(bist, cpu_init_detectedx);
 143 #endif
 144         real_main(bist, cpu_init_detectedx);
 145
 146 }
 147
 148 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 149 {
 150         static const struct mem_controller cpu[] = {
 151                 {
 152                         .node_id = 0,
 153                         .f0 = PCI_DEV(0, 0x18, 0),
 154                         .f1 = PCI_DEV(0, 0x18, 1),
 155                         .f2 = PCI_DEV(0, 0x18, 2),
 156                         .f3 = PCI_DEV(0, 0x18, 3),
 157                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 158                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 159                 },
 160 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 161                 {
 162                         .node_id = 1,
 163                         .f0 = PCI_DEV(0, 0x19, 0),
 164                         .f1 = PCI_DEV(0, 0x19, 1),
 165                         .f2 = PCI_DEV(0, 0x19, 2),
 166                         .f3 = PCI_DEV(0, 0x19, 3),
 167                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 168                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 169                 },
 170 #endif
 171         };
 172
 173         int needs_reset;
 174
 175         if (bist == 0) {
 176                 init_cpus(cpu_init_detectedx);
 177         }
 178
 179
 180         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 181         uart_init();
 182         console_init();
 183
 184         /* Halt if there was a built in self test failure */
 185         report_bist_failure(bist);
 186
 187         setup_default_resource_map();
 188
 189         needs_reset = setup_coherent_ht_domain();
 190
 191 #if CONFIG_LOGICAL_CPUS==1
 192         // It is said that we should start core1 after all core0 launched
 193         start_other_cores();
 194 #endif
 195         // automatically set that for you, but you might meet tight space
 196         needs_reset |= ht_setup_chains_x();
 197
 198         if (needs_reset) {
 199                 print_info("ht reset -\r\n");
 200                 soft_reset();
 201         }
 202
 203         enable_smbus();
 204
 205         memreset_setup();
 206         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 207
 208         post_cache_as_ram();
 209 }