src/mainboard/tyan/s2882/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #include <stdint.h>
   5 #include <string.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include <stdlib.h>
  12 #include "option_table.h"
  13 #include "pc80/mc146818rtc_early.c"
  14 #include "pc80/serial.c"
  15 #include "arch/i386/lib/console.c"
  16 #include "lib/ramtest.c"
  17
  18 #include <cpu/amd/model_fxx_rev.h>
  19 #include "northbridge/amd/amdk8/incoherent_ht.c"
  20 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  21 #include "northbridge/amd/amdk8/raminit.h"
  22 #include "cpu/amd/model_fxx/apic_timer.c"
  23 #include "lib/delay.c"
  24
  25 #include "cpu/x86/lapic/boot_cpu.c"
  26 #include "northbridge/amd/amdk8/reset_test.c"
  27 #include "northbridge/amd/amdk8/debug.c"
  28 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  29
  30 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  31 #include "cpu/x86/bist.h"
  32
  33 #include "northbridge/amd/amdk8/setup_resource_map.c"
  34
  35 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  36
  37 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  38
  39 static void memreset_setup(void)
  40 {
  41    if (is_cpu_pre_c0()) {
  42         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  43    }
  44    else {
  45         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  46    }
  47         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  48 }
  49
  50 static void memreset(int controllers, const struct mem_controller *ctrl)
  51 {
  52    if (is_cpu_pre_c0()) {
  53         udelay(800);
  54         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  55         udelay(90);
  56    }
  57 }
  58
  59 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  60 {
  61         /* nothing to do */
  62 }
  63
  64 static inline int spd_read_byte(unsigned device, unsigned address)
  65 {
  66         return smbus_read_byte(device, address);
  67 }
  68
  69 #define QRANK_DIMM_SUPPORT 1
  70
  71 #include "northbridge/amd/amdk8/raminit.c"
  72 #include "northbridge/amd/amdk8/resourcemap.c"
  73 #include "northbridge/amd/amdk8/coherent_ht.c"
  74 #include "lib/generic_sdram.c"
  75
  76 #if CONFIG_LOGICAL_CPUS==1
  77 #define SET_NB_CFG_54 1
  78 #endif
  79 #include "cpu/amd/dualcore/dualcore.c"
  80
  81 #define FIRST_CPU  1
  82 #define SECOND_CPU 1
  83 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  84
  85 #include "cpu/amd/car/copy_and_run.c"
  86
  87 #include "cpu/amd/car/post_cache_as_ram.c"
  88
  89 #include "cpu/amd/model_fxx/init_cpus.c"
  90
  91
  92 #if CONFIG_USE_FALLBACK_IMAGE == 1
  93
  94 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  95 #include "northbridge/amd/amdk8/early_ht.c"
  96
  97 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
  98 {
  99         unsigned last_boot_normal_x = last_boot_normal();
 100
 101         /* Is this a cpu only reset? or Is this a secondary cpu? */
 102         if ((cpu_init_detectedx) || (!boot_cpu())) {
 103                 if (last_boot_normal_x) {
 104                         goto normal_image;
 105                 } else {
 106                         goto fallback_image;
 107                 }
 108         }
 109
 110         /* Nothing special needs to be done to find bus 0 */
 111         /* Allow the HT devices to be found */
 112
 113         enumerate_ht_chain();
 114
 115         amd8111_enable_rom();
 116
 117         /* Is this a deliberate reset by the bios */
 118         if (bios_reset_detected() && last_boot_normal_x) {
 119                 goto normal_image;
 120         }
 121         /* This is the primary cpu how should I boot? */
 122         else if (do_normal_boot()) {
 123                 goto normal_image;
 124         }
 125         else {
 126                 goto fallback_image;
 127         }
 128  normal_image:
 129         __asm__ volatile ("jmp __normal_image"
 130                 : /* outputs */
 131                 : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
 132                 );
 133
 134  fallback_image:
 135         ;
 136 }
 137 #endif
 138
 139 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 140
 141 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 142 {
 143
 144 #if CONFIG_USE_FALLBACK_IMAGE == 1
 145         failover_process(bist, cpu_init_detectedx);
 146 #endif
 147         real_main(bist, cpu_init_detectedx);
 148
 149 }
 150
 151 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 152 {
 153         static const struct mem_controller cpu[] = {
 154                 {
 155                         .node_id = 0,
 156                         .f0 = PCI_DEV(0, 0x18, 0),
 157                         .f1 = PCI_DEV(0, 0x18, 1),
 158                         .f2 = PCI_DEV(0, 0x18, 2),
 159                         .f3 = PCI_DEV(0, 0x18, 3),
 160                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 161                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 162                 },
 163 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 164                 {
 165                         .node_id = 1,
 166                         .f0 = PCI_DEV(0, 0x19, 0),
 167                         .f1 = PCI_DEV(0, 0x19, 1),
 168                         .f2 = PCI_DEV(0, 0x19, 2),
 169                         .f3 = PCI_DEV(0, 0x19, 3),
 170                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 171                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 172                 },
 173 #endif
 174         };
 175
 176         int needs_reset;
 177
 178         if (bist == 0) {
 179                 init_cpus(cpu_init_detectedx);
 180         }
 181
 182
 183         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 184         uart_init();
 185         console_init();
 186
 187         /* Halt if there was a built in self test failure */
 188         report_bist_failure(bist);
 189
 190         setup_default_resource_map();
 191
 192         needs_reset = setup_coherent_ht_domain();
 193
 194 #if CONFIG_LOGICAL_CPUS==1
 195         // It is said that we should start core1 after all core0 launched
 196         start_other_cores();
 197 #endif
 198         // automatically set that for you, but you might meet tight space
 199         needs_reset |= ht_setup_chains_x();
 200
 201         if (needs_reset) {
 202                 print_info("ht reset -\r\n");
 203                 soft_reset();
 204         }
 205
 206         enable_smbus();
 207
 208         memreset_setup();
 209         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 210
 211         post_cache_as_ram();
 212
 213 }