src/mainboard/arima/hdama/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <stdlib.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "lib/ramtest.c"
  16
  17 #include <cpu/amd/model_fxx_rev.h>
  18 #include "northbridge/amd/amdk8/incoherent_ht.c"
  19 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  20 #include "northbridge/amd/amdk8/raminit.h"
  21 #include "cpu/amd/model_fxx/apic_timer.c"
  22 #include "lib/delay.c"
  23
  24 #include "cpu/x86/lapic/boot_cpu.c"
  25 #include "northbridge/amd/amdk8/reset_test.c"
  26 #include "northbridge/amd/amdk8/debug.c"
  27 #include "superio/nsc/pc87360/pc87360_early_serial.c"
  28
  29 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  30 #include "cpu/x86/bist.h"
  31
  32 #include "northbridge/amd/amdk8/setup_resource_map.c"
  33
  34 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  35
  36 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  37
  38 /*
  39  * GPIO28 of 8111 will control H0_MEMRESET_L
  40  * GPIO29 of 8111 will control H1_MEMRESET_L
  41  */
  42 static void memreset_setup(void)
  43 {
  44         if (is_cpu_pre_c0()) {
  45                 /* Set the memreset low */
  46                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  47                 /* Ensure the BIOS has control of the memory lines */
  48                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  49         }
  50         else {
  51                 /* Ensure the CPU has controll of the memory lines */
  52                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  53         }
  54 }
  55
  56 static void memreset(int controllers, const struct mem_controller *ctrl)
  57 {
  58         if (is_cpu_pre_c0()) {
  59                 udelay(800);
  60                 /* Set memreset_high */
  61                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  62                 udelay(90);
  63         }
  64 }
  65
  66 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  67 {
  68         /* nothing to do */
  69 }
  70
  71 static inline int spd_read_byte(unsigned device, unsigned address)
  72 {
  73         return smbus_read_byte(device, address);
  74 }
  75
  76 #define QRANK_DIMM_SUPPORT 1
  77
  78 #include "northbridge/amd/amdk8/raminit.c"
  79 #include "northbridge/amd/amdk8/resourcemap.c"
  80 #include "northbridge/amd/amdk8/coherent_ht.c"
  81 #include "lib/generic_sdram.c"
  82
  83 #if CONFIG_LOGICAL_CPUS==1
  84 #define SET_NB_CFG_54 1
  85 #endif
  86 #include "cpu/amd/dualcore/dualcore.c"
  87
  88 #define FIRST_CPU  1
  89 #define SECOND_CPU 1
  90 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  91
  92 #include "cpu/amd/car/copy_and_run.c"
  93
  94 #include "cpu/amd/car/post_cache_as_ram.c"
  95
  96 #include "cpu/amd/model_fxx/init_cpus.c"
  97
  98 #if CONFIG_USE_FALLBACK_IMAGE == 1
  99
 100 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 101 #include "northbridge/amd/amdk8/early_ht.c"
 102
 103 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 104 {
 105         unsigned last_boot_normal_x = last_boot_normal();
 106
 107         /* Is this a cpu only reset? or Is this a secondary cpu? */
 108         if ((cpu_init_detectedx) || (!boot_cpu())) {
 109                 if (last_boot_normal_x) {
 110                         goto normal_image;
 111                 } else {
 112                         goto fallback_image;
 113                 }
 114         }
 115
 116         /* Nothing special needs to be done to find bus 0 */
 117         /* Allow the HT devices to be found */
 118
 119         enumerate_ht_chain();
 120
 121         amd8111_enable_rom();
 122
 123         /* Is this a deliberate reset by the bios */
 124         if (bios_reset_detected() && last_boot_normal_x) {
 125                 goto normal_image;
 126         }
 127         /* This is the primary cpu how should I boot? */
 128         else if (do_normal_boot()) {
 129                 goto normal_image;
 130         }
 131         else {
 132                 goto fallback_image;
 133         }
 134  normal_image:
 135         __asm__ volatile ("jmp __normal_image"
 136                 : /* outputs */
 137                 : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
 138                 );
 139
 140  fallback_image:
 141         ;
 142 }
 143 #endif
 144
 145 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 146
 147 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 148 {
 149
 150 #if CONFIG_USE_FALLBACK_IMAGE == 1
 151         failover_process(bist, cpu_init_detectedx);
 152 #endif
 153         real_main(bist, cpu_init_detectedx);
 154 }
 155
 156 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 157 {
 158         static const uint16_t spd_addr [] = {
 159                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 160                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 161 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 162                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 163                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 164 #endif
 165         };
 166
 167         int needs_reset;
 168         unsigned bsp_apicid = 0;
 169         struct mem_controller ctrl[8];
 170         unsigned nodes;
 171
 172         if (bist == 0) {
 173                 bsp_apicid = init_cpus(cpu_init_detectedx);
 174         }
 175
 176         pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 177         uart_init();
 178         console_init();
 179
 180         /* Halt if there was a built in self test failure */
 181         report_bist_failure(bist);
 182
 183         setup_default_resource_map();
 184
 185         needs_reset = setup_coherent_ht_domain();
 186
 187 #if CONFIG_LOGICAL_CPUS==1
 188         // It is said that we should start core1 after all core0 launched
 189         start_other_cores();
 190         wait_all_other_cores_started(bsp_apicid);
 191 #endif
 192         /* This is needed to be able to call udelay().  It could be moved to
 193          * memreset_setup, since udelay is called in memreset. */
 194         init_timer();
 195
 196         // automatically set that for you, but you might meet tight space
 197         needs_reset |= ht_setup_chains_x();
 198
 199         if (needs_reset) {
 200                 print_info("ht reset -\r\n");
 201                 soft_reset();
 202         }
 203
 204         allow_all_aps_stop(bsp_apicid);
 205
 206         nodes = get_nodes();
 207
 208         fill_mem_ctrl(nodes, ctrl, spd_addr);
 209
 210         enable_smbus();
 211
 212         memreset_setup();
 213
 214         sdram_initialize(nodes, ctrl);
 215
 216         post_cache_as_ram();
 217 }