2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
13 sys_res : in std_logic;
14 sys_clk : in std_logic;
15 -- result : out gp_register_t;
16 -- reg_wr_data : out gp_register_t
18 bus_tx : out std_logic
23 architecture behav of core_top is
25 signal jump_result : instruction_addr_t;
26 signal jump_result_pin : instruction_addr_t;
27 signal prediction_result_pin : instruction_addr_t;
28 signal branch_prediction_bit_pin : std_logic;
29 signal alu_jump_bit_pin : std_logic;
30 signal instruction_pin : instruction_word_t;
31 signal prog_cnt_pin : instruction_addr_t;
33 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
34 signal reg_wr_data_pin : gp_register_t;
35 signal reg_we_pin : std_logic;
36 signal to_next_stage : dec_op;
38 -- signal reg1_rd_data_pin : gp_register_t;
39 -- signal reg2_rd_data_pin : gp_register_t;
41 signal result_pin : gp_register_t;--reg
42 signal result_addr_pin : gp_addr_t;--reg
43 signal addr_pin : word_t; --memaddr
44 signal data_pin : gp_register_t; --mem data --ureg
45 signal alu_jump_pin : std_logic;--reg
46 signal brpr_pin : std_logic; --reg
47 signal wr_en_pin : std_logic;--regop --reg
48 signal dmem_pin : std_logic;--memop
49 signal dmem_wr_en_pin : std_logic;
50 signal hword_pin : std_logic;
51 signal byte_s_pin : std_logic;
53 signal gpm_in_pin : extmod_rec;
54 signal gpm_out_pin : gp_register_t;
55 signal nop_pin : std_logic;
60 fetch_st : fetch_stage
69 clk => sys_clk, --: in std_logic;
70 reset => sys_res, --: in std_logic;
73 jump_result => jump_result_pin, --: in instruction_addr_t;
74 prediction_result => prediction_result_pin, --: in instruction_addr_t;
75 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
76 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
79 instruction => instruction_pin, --: out instruction_word_t
80 prog_cnt => prog_cnt_pin
83 decode_st : decode_stage
93 clk => sys_clk, --: in std_logic;
94 reset => sys_res, -- : in std_logic;
97 instruction => instruction_pin, --: in instruction_word_t;
98 prog_cnt => prog_cnt_pin,
99 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
100 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
101 reg_we => reg_we_pin, --: in std_logic;
105 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
106 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
107 to_next_stage => to_next_stage
110 exec_st : execute_stage
112 port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
113 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
115 writeback_st : writeback_stage
116 generic map('0', '1')
117 port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
118 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
119 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx);
125 --init : process(all)
128 -- jump_result_pin <= (others => '0');
129 -- alu_jump_bit_pin <= '0';
130 -- reg_w_addr_pin <= (others => '0');
131 -- reg_wr_data_pin <= (others => '0');
132 -- reg_we_pin <= '0';
136 -- result <= result_pin;
137 nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
139 jump_result <= prog_cnt_pin; --jump_result_pin;
142 -- reg_wr_data <= reg_wr_data_pin;