--- /dev/null
+.text
+ ldi r5, 0x5a
+ ldi r0, 0x100b
+ stw r5, 0(r0)
vcom -work work ../src/r2_w_ram.vhd
vcom -work work ../src/r2_w_ram_b.vhd
vcom -work work ../src/common_pkg.vhd
+vcom -work work ../src/extension_pkg.vhd
vcom -work work ../src/core_pkg.vhd
vcom -work work ../src/decoder.vhd
vcom -work work ../src/decoder_b.vhd
vcom -work work ../src/decode_stage_b.vhd
vcom -work work ../src/alu_pkg.vhd
-vcom -work work ../src/extension_pkg.vhd
vcom -work work ../src/exec_op.vhd
reg_we : out std_logic;
reg_addr : out gp_addr_t;
jump_addr : out instruction_addr_t;
- jump : out std_logic
+ jump : out std_logic;
+ -- same here
+ bus_tx : out std_logic
);
end component writeback_stage;
port(
--System input pins
sys_clk : in std_logic;
- sys_res : in std_logic;
-- result : out gp_register_t;
- jump_result : out instruction_addr_t
-- reg_wr_data : out gp_register_t
-
+ -- uart
+ bus_tx : out std_logic
);
end core_top;
architecture behav of core_top is
+ signal jump_result : instruction_addr_t;
+ signal sys_res : std_logic;
signal jump_result_pin : instruction_addr_t;
signal prediction_result_pin : instruction_addr_t;
signal branch_prediction_bit_pin : std_logic;
generic map('0', '1')
port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx);
nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
jump_result <= prog_cnt_pin; --jump_result_pin;
+ sys_res <= '1';
-- reg_wr_data <= reg_wr_data_pin;
end behav;
constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB";
constant EXT_TIMER_ADDR: ext_addrid_t := x"FFFFFFC";
constant EXT_AC97_ADDR: ext_addrid_t := x"FFFFFFD";
---constant EXT_UART_ADDR: ext_addrid_t := x"FFFFFFE";
-constant EXT_UART_ADDR: ext_addrid_t := x"0000000";
+-- constant EXT_UART_ADDR: ext_addrid_t := x"FFFFFFE";
+constant EXT_UART_ADDR: ext_addrid_t := x"0000100";
constant EXT_GPMP_ADDR: ext_addrid_t := x"FFFFFFF";
component extension_gpm is
-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
-gwriten : process (ext_reg,tx_rdy)
+gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int)
variable tmp_data : gp_register_t;
begin
+
+ w1_st_co_nxt <= w1_st_co;
+ w2_uart_config_nxt <= w2_uart_config;
+ w3_uart_send_nxt <= w3_uart_send;
+ w4_uart_receive_nxt <= w4_uart_receive;
+
if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
tmp_data := (others =>'0');
if ext_reg.byte_en(0) = '1' then
w4_uart_receive_nxt <= tmp_data;
when others => null;
end case;
- else
- w1_st_co_nxt <= w1_st_co;
- w2_uart_config_nxt <= w2_uart_config;
- w3_uart_send_nxt <= w3_uart_send;
- w4_uart_receive_nxt <= w4_uart_receive;
end if;
if tx_rdy = '1' and tx_rdy_int = '0' then
end process gwriten;
-gread : process (clk,ext_reg)
+gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
variable tmp_data : gp_register_t;
-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
-dataprocess : process (ext_reg,tx_rdy)
+dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
begin
--CLKs
constant CLK_FREQ_MHZ : real := 33.33;
constant BAUD_RATE : integer := 115200;
-constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
+--constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
+constant CLK_PER_BAUD : integer := 16330000;
component extension_uart is
--some modules won't need all inputs/outputs
wait until sys_res_n_pin = '1';
- icwait(100000);
+ icwait(1000000000);
---------------------------------------------------------------------------
-- exit testbench
-- r0 = 0, r1 = 1, r2 = 3, r3 = A
signal ram : RAM_TYPE := (
-
-
- 0 => "11101101000000000000000001011000", -- r0 = 11
- 1 => "11101101000010000000000000111000", -- r1 = 7
- 2 => "11100111100010000000000000000000", --stw
- 3 => "11101101000000000000000000011000", -- r0 = 3
- 4 => "11101101000010000000000001001000", -- r1 = 9
- 5 => "11100111000010000000000000000000", --ldw
- 6 => "11101101000000000000000000011000", -- r0 = 3
- 7 => "11101101000010000000000001001000", -- r1 = 9
--8 => "11100111100010000000000000000000", --stw
-- 0 => "11101101000000000000000000000000", --ldi
-- 1 => "11101101001000000000000000000000", --ldi
process(clk)
begin
if rising_edge(clk) then
- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+ -- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+ case rd_addr is
+ when "00000000000" => data_out <= x"ed2802d0"; -- ldi r5, 0x5a;;
+ when "00000000100" => data_out <= x"ed008058"; -- ldi r0, 0x100b;;
+ when "00000001000" => data_out <= x"e7a80000"; -- stw r5, 0(r0);;
+ when others => data_out <= x"07a80000";
+ end case;
if wr_en = '1' then
ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
----------------------------------------------------------------------------------\r
--- Filename : rs232_tx_arc.vhd\r
--- ========== \r
--- \r
--- Beschreibung : Versand von Daten ueber die RS232 Schnittstelle\r
--- ==============\r
---\r
--- Autoren : Martin Perner, Schwarz Manfred\r
--- =========\r
-----------------------------------------------------------------------------------\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.numeric_std.all;\r
-\r
-use work.common_pkg.all;\r
-use work.core_pkg.all;\r
-use work.extension_uart_pkg.all;\r
-\r
-architecture beh of rs232_tx is\r
- -- definierern der intern verwendeten Signale\r
- type STATE_TYPE is (IDLE,SEND);\r
- signal state, state_next : STATE_TYPE;\r
- signal bus_tx_int, bus_tx_nxt : std_logic := '1';\r
- signal baud_cnt,baud_cnt_next : integer := CLK_PER_BAUD;\r
- signal cnt, cnt_next : natural range 0 to 11 := 0;\r
- signal idle_sig, idle_sig_next : std_logic := '0';\r
- \r
-begin\r
- -- syncronisierungs Prozess\r
- rs232_tx_syn : process(sys_clk, sys_res_n)\r
- begin\r
- if (sys_res_n = RESET_VALUE) then\r
- -- reset\r
- cnt <= 0;\r
- baud_cnt <= 0;\r
- state <= IDLE;\r
- idle_sig <= '0';\r
- bus_tx_int <= '1';\r
- elsif rising_edge(sys_clk) then\r
- -- sync Zustand, uebernehmen der next-Signale\r
- baud_cnt <= baud_cnt_next;\r
- cnt <= cnt_next;\r
- state <= state_next;\r
- idle_sig <= idle_sig_next;\r
- bus_tx_int <= bus_tx_nxt;\r
- end if;\r
- end process;\r
-\r
- bus_tx <= bus_tx_int;\r
-\r
- -- Zustandsmaschienen Prozess\r
- rs232_tx_state : process(state, new_tx_data, idle_sig)\r
- begin\r
- state_next <= state;\r
- case state is\r
- when IDLE =>\r
- -- wenn neue Sendedaten anliegen wird in den Zustand SEND gewechselt\r
- if new_tx_data = '1' then\r
- state_next <= SEND;\r
- end if;\r
- when SEND =>\r
- -- wenn das Byte inklusive Start- und Stopbit versendet wurde, geht \r
- -- der Prozess wieder in den IDLE Zustand.\r
- if idle_sig = '1' then\r
- state_next <= IDLE;\r
- end if;\r
- end case;\r
- end process;\r
-\r
- -- Ausgabe Logik\r
- rs232_tx_baud : process(sys_clk, sys_res_n, state, baud_cnt, cnt, tx_data, bus_tx_int)\r
- begin \r
- -- Solang idle_sig auf 0 ist wird im SEND Zustand verblieben\r
- idle_sig_next <= '0';\r
- bus_tx_nxt <= bus_tx_int;\r
- cnt_next <= cnt;\r
- baud_cnt_next <= baud_cnt;\r
-\r
- case state is\r
- when IDLE =>\r
- -- tx-Signale im idle Zustand halten\r
- tx_rdy <= '1';\r
- baud_cnt_next <= CLK_PER_BAUD;\r
- when SEND =>\r
- -- Signalisiert dass gerade ein Byte versendet wird \r
- tx_rdy <= '0';\r
- -- Counter erhoehen um die Zeit einer Bitdauer abzuwarten\r
- baud_cnt_next <= baud_cnt + 1;\r
- if baud_cnt = CLK_PER_BAUD then \r
- -- wenn die Bitdauer erreicht ist, Counter reseten\r
- baud_cnt_next <= 0;\r
- -- Counter um die einzelen Bits zu versenden\r
- cnt_next <= cnt + 1;\r
- case cnt is\r
- when 0 =>\r
- -- counter = 0 => Startbit versenden\r
- bus_tx_nxt <= '0';\r
- when 9 =>\r
- -- counter = 9 => Stopbit versenden\r
- bus_tx_nxt <= '1';\r
- -- stop_bit 0 heißt 1 stop bit\r
- if stop_bit = '0' then \r
- cnt_next <= 0;\r
- idle_sig_next <= '1';\r
- end if; \r
- when 10 =>\r
- bus_tx_nxt <= '1';\r
- -- stop_bit 1 heißt 2 stop bits\r
- if stop_bit = '1' then \r
- cnt_next <= 0;\r
- -- Signalisieren dass der Sendevorgang beendet ist\r
- idle_sig_next <= '1';\r
- end if;\r
- when others =>\r
- -- counter von 1 bis 8 => Datenbits versenden\r
- bus_tx_nxt <= tx_data(cnt-1);\r
- end case;\r
- end if;\r
- end case;\r
- end process;\r
-\r
-end architecture beh;\r
+---------------------------------------------------------------------------------
+-- Filename : rs232_tx_arc.vhd
+-- ==========
+--
+-- Beschreibung : Versand von Daten ueber die RS232 Schnittstelle
+-- ==============
+--
+-- Autoren : Martin Perner, Schwarz Manfred
+-- =========
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+use work.extension_uart_pkg.all;
+
+architecture beh of rs232_tx is
+ -- definierern der intern verwendeten Signale
+ type STATE_TYPE is (IDLE,SEND);
+ signal state, state_next : STATE_TYPE;
+ signal bus_tx_int, bus_tx_nxt : std_logic := '1';
+ signal baud_cnt,baud_cnt_next : integer := CLK_PER_BAUD;
+ signal cnt, cnt_next : natural range 0 to 11 := 0;
+ signal idle_sig, idle_sig_next : std_logic := '0';
+
+begin
+ -- syncronisierungs Prozess
+ rs232_tx_syn : process(sys_clk, sys_res_n)
+ begin
+ if (sys_res_n = RESET_VALUE) then
+ -- reset
+ cnt <= 0;
+ baud_cnt <= 0;
+ state <= IDLE;
+ idle_sig <= '0';
+ bus_tx_int <= '1';
+ elsif rising_edge(sys_clk) then
+ -- sync Zustand, uebernehmen der next-Signale
+ baud_cnt <= baud_cnt_next;
+ cnt <= cnt_next;
+ state <= state_next;
+ idle_sig <= idle_sig_next;
+ bus_tx_int <= bus_tx_nxt;
+ end if;
+ end process;
+
+ bus_tx <= bus_tx_int;
+
+ -- Zustandsmaschienen Prozess
+ rs232_tx_state : process(state, new_tx_data, idle_sig)
+ begin
+ state_next <= state;
+ case state is
+ when IDLE =>
+ -- wenn neue Sendedaten anliegen wird in den Zustand SEND gewechselt
+ if new_tx_data = '1' then
+ state_next <= SEND;
+ end if;
+ when SEND =>
+ -- wenn das Byte inklusive Start- und Stopbit versendet wurde, geht
+ -- der Prozess wieder in den IDLE Zustand.
+ if idle_sig = '1' then
+ state_next <= IDLE;
+ end if;
+ end case;
+ end process;
+
+ -- Ausgabe Logik
+ rs232_tx_baud : process(sys_clk, sys_res_n, state, baud_cnt, cnt, tx_data, bus_tx_int,stop_bit)
+ begin
+ -- Solang idle_sig auf 0 ist wird im SEND Zustand verblieben
+ idle_sig_next <= '0';
+ bus_tx_nxt <= bus_tx_int;
+ cnt_next <= cnt;
+ baud_cnt_next <= baud_cnt;
+
+ case state is
+ when IDLE =>
+ -- tx-Signale im idle Zustand halten
+ tx_rdy <= '1';
+ baud_cnt_next <= CLK_PER_BAUD;
+ when SEND =>
+ -- Signalisiert dass gerade ein Byte versendet wird
+ tx_rdy <= '0';
+ -- Counter erhoehen um die Zeit einer Bitdauer abzuwarten
+ baud_cnt_next <= baud_cnt + 1;
+ if baud_cnt = CLK_PER_BAUD then
+ -- wenn die Bitdauer erreicht ist, Counter reseten
+ baud_cnt_next <= 0;
+ -- Counter um die einzelen Bits zu versenden
+ cnt_next <= cnt + 1;
+ case cnt is
+ when 0 =>
+ -- counter = 0 => Startbit versenden
+ bus_tx_nxt <= '0';
+ when 9 =>
+ -- counter = 9 => Stopbit versenden
+ bus_tx_nxt <= '1';
+ -- stop_bit 0 heißt 1 stop bit
+ if stop_bit = '0' then
+ cnt_next <= 0;
+ idle_sig_next <= '1';
+ end if;
+ when 10 =>
+ bus_tx_nxt <= '1';
+ -- stop_bit 1 heißt 2 stop bits
+ if stop_bit = '1' then
+ cnt_next <= 0;
+ -- Signalisieren dass der Sendevorgang beendet ist
+ idle_sig_next <= '1';
+ end if;
+ when others =>
+ -- counter von 1 bis 8 => Datenbits versenden
+ bus_tx_nxt <= tx_data(cnt-1);
+ end case;
+ end if;
+ end case;
+ end process;
+
+end architecture beh;
reg_we : out std_logic;
reg_addr : out gp_addr_t;
jump_addr : out instruction_addr_t;
- jump : out std_logic
+ jump : out std_logic;
+ -- hallo stefan mir adden da jetzt mal schnell an uart port :D
+ bus_tx : out std_logic
);
end writeback_stage;
signal ext_uart,ext_timer,ext_gpmp : extmod_rec;
-signal bus_tx,sel_nxt :std_logic;
+signal sel_nxt :std_logic;
--- /dev/null
+db/
+incremental_db
+work/
--- /dev/null
+Assembler report for dt
+Thu Dec 16 16:55:03 2010
+Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: dt.sof
+ 6. Assembler Device Options: dt.pof
+ 7. Assembler Device Options: dt.rbf
+ 8. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Thu Dec 16 16:55:03 2010 ;
+; Revision Name ; dt ;
+; Top-level Entity Name ; core_top ;
+; Family ; Cyclone ;
+; Device ; EP1C12Q240C8 ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option ; Setting ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Generate compressed bitstreams ; Off ; On ;
+; Generate Raw Binary File (.rbf) For Target Device ; On ; Off ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Compression mode ; Off ; Off ;
+; Clock source for configuration device ; Internal ; Internal ;
+; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
+; Divide clock frequency by ; 1 ; 1 ;
+; Auto user code ; Off ; Off ;
+; Use configuration device ; On ; On ;
+; Configuration device ; Auto ; Auto ;
+; Configuration device auto user code ; Off ; Off ;
+; Auto-increment JTAG user code for multiple configuration devices ; On ; On ;
+; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
+; Hexadecimal Output File start address ; 0 ; 0 ;
+; Hexadecimal Output File count direction ; Up ; Up ;
+; Release clears before tri-states ; Off ; Off ;
+; Auto-restart configuration after error ; On ; On ;
+; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------+
+; Assembler Generated Files ;
++---------------------------+
+; File Name ;
++---------------------------+
+; dt.sof ;
+; dt.pof ;
+; dt.rbf ;
++---------------------------+
+
+
++----------------------------------+
+; Assembler Device Options: dt.sof ;
++----------------+-----------------+
+; Option ; Setting ;
++----------------+-----------------+
+; Device ; EP1C12Q240C8 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x00162065 ;
++----------------+-----------------+
+
+
++----------------------------------+
+; Assembler Device Options: dt.pof ;
++--------------------+-------------+
+; Option ; Setting ;
++--------------------+-------------+
+; Device ; EPCS4 ;
+; JTAG usercode ; 0x00000000 ;
+; Checksum ; 0x03AC7869 ;
+; Compression Ratio ; 1 ;
++--------------------+-------------+
+
+
++----------------------------------+
+; Assembler Device Options: dt.rbf ;
++---------------------+------------+
+; Option ; Setting ;
++---------------------+------------+
+; Raw Binary File ; ;
+; Compression Ratio ; 1 ;
++---------------------+------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Assembler
+ Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+ Info: Processing started: Thu Dec 16 16:55:00 2010
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off dt -c dt
+Info: Assembler is generating device programming files
+Info: Quartus II Assembler was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 229 megabytes
+ Info: Processing ended: Thu Dec 16 16:55:03 2010
+ Info: Elapsed time: 00:00:03
+ Info: Total CPU time (on all processors): 00:00:02
+
+
--- /dev/null
+Thu Dec 16 16:55:06 2010
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+
+<pin_planner>
+ <pin_info>
+ </pin_info>
+ <buses>
+ </buses>
+ <group_file_association>
+ </group_file_association>
+ <pin_planner_file_specifies>
+ </pin_planner_file_specifies>
+</pin_planner>
--- /dev/null
+Fitter report for dt
+Thu Dec 16 16:54:58 2010
+Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Incremental Compilation Preservation Summary
+ 6. Incremental Compilation Partition Settings
+ 7. Incremental Compilation Placement Preservation
+ 8. Pin-Out File
+ 9. Fitter Resource Usage Summary
+ 10. Fitter Partition Statistics
+ 11. Input Pins
+ 12. Output Pins
+ 13. I/O Bank Usage
+ 14. All Package Pins
+ 15. Output Pin Default Load For Reported TCO
+ 16. Fitter Resource Utilization by Entity
+ 17. Delay Chain Summary
+ 18. Pad To Core Delay Chain Fanout
+ 19. Control Signals
+ 20. Global & Other Fast Signals
+ 21. Non-Global High Fan-Out Signals
+ 22. Fitter RAM Summary
+ 23. Interconnect Usage Summary
+ 24. LAB Logic Elements
+ 25. LAB-wide Signals
+ 26. LAB Signals Sourced
+ 27. LAB Signals Sourced Out
+ 28. LAB Distinct Inputs
+ 29. Fitter Device Options
+ 30. Estimated Delay Added for Hold Timing Summary
+ 31. Estimated Delay Added for Hold Timing Details
+ 32. Fitter Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------+
+; Fitter Summary ;
++-----------------------+-----------------------------------------------+
+; Fitter Status ; Successful - Thu Dec 16 16:54:57 2010 ;
+; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
+; Revision Name ; dt ;
+; Top-level Entity Name ; core_top ;
+; Family ; Cyclone ;
+; Device ; EP1C12Q240C8 ;
+; Timing Models ; Final ;
+; Total logic elements ; 398 / 12,060 ( 3 % ) ;
+; Total pins ; 2 / 173 ( 1 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
+; Total PLLs ; 0 / 2 ( 0 % ) ;
++-----------------------+-----------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++----------------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device ; EP1C12Q240C8 ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Device I/O Standard ; 3.3-V LVCMOS ; ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Use TimeQuest Timing Analyzer ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate full fit report during ECO compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
+; Limit to One Fitting Attempt ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Slow Slew Rate ; Off ; Off ;
+; PCI I/O ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Global Memory Control Signals ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Merge PLLs ; On ; On ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Stop After Congestion Map Generation ; Off ; Off ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
++----------------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation ;
++----------------------------+--------+
+; Processors ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 2 ;
+; Maximum allowed ; 1 ;
++----------------------------+--------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+------------------------+
+; Type ; Value ;
++---------------------+------------------------+
+; Placement (by node) ; ;
+; -- Requested ; 0 / 466 ( 0.00 % ) ;
+; -- Achieved ; 0 / 466 ( 0.00 % ) ;
+; ; ;
+; Routing (by net) ; ;
+; -- Requested ; 0 / 0 ( 0.00 % ) ;
+; -- Achieved ; 0 / 0 ( 0.00 % ) ;
++---------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Top ; 464 ; 0 ; N/A ; Source File ;
+; hard_block:auto_generated_inst ; 2 ; 0 ; N/A ; Source File ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /homes/burban/calu/dt/dt.pin.
+
+
++-------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+---------------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+---------------------------------------------+
+; Total logic elements ; 398 / 12,060 ( 3 % ) ;
+; -- Combinational with no register ; 257 ;
+; -- Register only ; 12 ;
+; -- Combinational with a register ; 129 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 105 ;
+; -- 3 input functions ; 195 ;
+; -- 2 input functions ; 80 ;
+; -- 1 input functions ; 4 ;
+; -- 0 input functions ; 2 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 298 ;
+; -- arithmetic mode ; 100 ;
+; -- qfbk mode ; 35 ;
+; -- register cascade mode ; 0 ;
+; -- synchronous clear/load mode ; 44 ;
+; -- asynchronous clear/load mode ; 0 ;
+; ; ;
+; Total registers ; 141 / 12,567 ( 1 % ) ;
+; Total LABs ; 48 / 1,206 ( 4 % ) ;
+; Logic elements in carry chains ; 104 ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 2 / 173 ( 1 % ) ;
+; -- Clock pins ; 1 / 2 ( 50 % ) ;
+; Global signals ; 1 ;
+; M4Ks ; 2 / 52 ( 4 % ) ;
+; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
+; Total RAM block bits ; 9,216 / 239,616 ( 4 % ) ;
+; PLLs ; 0 / 2 ( 0 % ) ;
+; Global clocks ; 1 / 8 ( 13 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI Blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 1% / 1% / 1% ;
+; Peak interconnect usage (total/H/V) ; 4% / 5% / 4% ;
+; Maximum fan-out node ; sys_clk ;
+; Maximum fan-out ; 143 ;
+; Highest non-global fan-out signal ; decode_stage:decode_st|rtw_rec.immediate[3] ;
+; Highest non-global fan-out ; 66 ;
+; Total fan-out ; 1487 ;
+; Average fan-out ; 3.68 ;
++---------------------------------------------+---------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics ;
++---------------------------------------------+--------------------+--------------------------------+
+; Statistic ; Top ; hard_block:auto_generated_inst ;
++---------------------------------------------+--------------------+--------------------------------+
+; Difficulty Clustering Region ; Low ; Low ;
+; ; ; ;
+; Total logic elements ; 398 ; 0 ;
+; -- Combinational with no register ; 257 ; 0 ;
+; -- Register only ; 12 ; 0 ;
+; -- Combinational with a register ; 129 ; 0 ;
+; ; ; ;
+; Logic element usage by number of LUT inputs ; ; ;
+; -- 4 input functions ; 0 ; 0 ;
+; -- 3 input functions ; 0 ; 0 ;
+; -- 2 input functions ; 0 ; 0 ;
+; -- 1 input functions ; 0 ; 0 ;
+; -- 0 input functions ; 0 ; 0 ;
+; ; ; ;
+; Logic elements by mode ; ; ;
+; -- normal mode ; 0 ; 0 ;
+; -- arithmetic mode ; 0 ; 0 ;
+; -- qfbk mode ; 0 ; 0 ;
+; -- register cascade mode ; 0 ; 0 ;
+; -- synchronous clear/load mode ; 0 ; 0 ;
+; -- asynchronous clear/load mode ; 0 ; 0 ;
+; ; ; ;
+; Total registers ; 141 / 6030 ( 2 % ) ; 0 / 6030 ( 0 % ) ;
+; Virtual pins ; 0 ; 0 ;
+; I/O pins ; 2 ; 0 ;
+; DSP block 9-bit elements ; 0 ; 0 ;
+; Total memory bits ; 512 ; 0 ;
+; Total RAM block bits ; 9216 ; 0 ;
+; M4K ; 2 / 52 ( 3 % ) ; 0 / 52 ( 0 % ) ;
+; ; ; ;
+; Connections ; ; ;
+; -- Input Connections ; 0 ; 0 ;
+; -- Registered Input Connections ; 0 ; 0 ;
+; -- Output Connections ; 0 ; 0 ;
+; -- Registered Output Connections ; 0 ; 0 ;
+; ; ; ;
+; Internal Connections ; ; ;
+; -- Total Connections ; 1572 ; 0 ;
+; -- Registered Connections ; 590 ; 0 ;
+; ; ; ;
+; External Connections ; ; ;
+; -- Top ; 0 ; 0 ;
+; -- hard_block:auto_generated_inst ; 0 ; 0 ;
+; ; ; ;
+; Partition Interface ; ; ;
+; -- Input Ports ; 1 ; 0 ;
+; -- Output Ports ; 1 ; 0 ;
+; -- Bidir Ports ; 0 ; 0 ;
+; ; ; ;
+; Registered Ports ; ; ;
+; -- Registered Input Ports ; 0 ; 0 ;
+; -- Registered Output Ports ; 0 ; 0 ;
+; ; ; ;
+; Port Connectivity ; ; ;
+; -- Input Ports driven by GND ; 0 ; 0 ;
+; -- Output Ports driven by GND ; 0 ; 0 ;
+; -- Input Ports driven by VCC ; 0 ; 0 ;
+; -- Output Ports driven by VCC ; 0 ; 0 ;
+; -- Input Ports with no Source ; 0 ; 0 ;
+; -- Output Ports with no Source ; 0 ; 0 ;
+; -- Input Ports with no Fanout ; 0 ; 0 ;
+; -- Output Ports with no Fanout ; 0 ; 0 ;
++---------------------------------------------+--------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; sys_clk ; 152 ; 3 ; 53 ; 15 ; 2 ; 143 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
++--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
+; bus_tx ; 166 ; 3 ; 53 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 10 pF ; - ; - ;
++--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
+
+
++----------------------------------------------------------+
+; I/O Bank Usage ;
++----------+----------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+----------------+---------------+--------------+
+; 1 ; 2 / 44 ( 5 % ) ; 3.3V ; -- ;
+; 2 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ;
+; 3 ; 2 / 45 ( 4 % ) ; 3.3V ; -- ;
+; 4 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ;
++----------+----------------+---------------+--------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; 1 ; 0 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 2 ; 1 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 7 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 8 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 14 ; 11 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 15 ; 12 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 16 ; 13 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 17 ; 14 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 18 ; 15 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 19 ; 16 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 20 ; 17 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 21 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 23 ; 28 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 24 ; 29 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; On ;
+; 25 ; 30 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
+; 26 ; 31 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; 27 ; ; ; VCCA_PLL1 ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 28 ; 32 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 29 ; 33 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 30 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 31 ; ; ; GNDG_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 32 ; 34 ; 1 ; ^nCEO ; ; ; ; -- ; ; -- ; -- ;
+; 33 ; 35 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; 34 ; 36 ; 1 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; 35 ; 37 ; 1 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; 36 ; 38 ; 1 ; ^DCLK ; bidir ; ; ; -- ; ; -- ; -- ;
+; 37 ; 39 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; On ;
+; 38 ; 40 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 39 ; 41 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 40 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 41 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 42 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 43 ; 54 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 44 ; 55 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 45 ; 56 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 46 ; 57 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 47 ; 58 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 48 ; 59 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 49 ; 60 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 50 ; 61 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 51 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 52 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 53 ; 62 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 54 ; 63 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 55 ; 64 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 56 ; 65 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 57 ; 66 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 58 ; 67 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 59 ; 68 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 60 ; 69 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 61 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 62 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 63 ; 72 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 64 ; 73 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 65 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 66 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 67 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 68 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 69 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 70 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 71 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 72 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 73 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 74 ; 79 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 75 ; 80 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 76 ; 81 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 77 ; 82 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 78 ; 83 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 79 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 80 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 81 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 82 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 83 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 84 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 85 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 86 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 87 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 88 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 89 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 90 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 91 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 92 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 93 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 94 ; 103 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 95 ; 104 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 96 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 97 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 98 ; 106 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 99 ; 107 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 100 ; 108 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 101 ; 109 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 102 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 103 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 104 ; 118 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 105 ; 119 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 106 ; 120 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 107 ; 121 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 108 ; 122 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 109 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 110 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 112 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 113 ; 123 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 114 ; 124 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 115 ; 125 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 116 ; 126 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 117 ; 127 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 118 ; 128 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 119 ; 129 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 120 ; 130 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 121 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 122 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 123 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 124 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 125 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 126 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 127 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 128 ; 138 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 129 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 130 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 131 ; 139 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 132 ; 140 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 133 ; 141 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 134 ; 142 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 135 ; 143 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 136 ; 144 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 137 ; 145 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 138 ; 146 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 139 ; 147 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 140 ; 148 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 141 ; 149 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 142 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 143 ; 160 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 144 ; 161 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 145 ; 162 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; 146 ; 163 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; 147 ; 164 ; 3 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; 148 ; 165 ; 3 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; 149 ; 166 ; 3 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; 150 ; ; ; GNDG_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 151 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 152 ; 167 ; 3 ; sys_clk ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 153 ; 168 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 154 ; ; ; VCCA_PLL2 ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 155 ; 169 ; 3 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; 156 ; 170 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 157 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 158 ; 180 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 159 ; 181 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 160 ; 182 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 161 ; 183 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 162 ; 184 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 163 ; 185 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 164 ; 186 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 165 ; 187 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 166 ; 188 ; 3 ; bus_tx ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 167 ; 189 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 168 ; 190 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 169 ; 191 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 170 ; 192 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 171 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 172 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 173 ; 193 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 174 ; 194 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 175 ; 195 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 176 ; 196 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 177 ; 197 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 178 ; 198 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 179 ; 199 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 180 ; 200 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 181 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 182 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 183 ; 203 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 184 ; 204 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 185 ; 205 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 186 ; 206 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 187 ; 207 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 188 ; 208 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 189 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 190 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 191 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 192 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 193 ; 209 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 194 ; 210 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 195 ; 211 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 196 ; 212 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 197 ; 213 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 198 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 199 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 200 ; 222 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 201 ; 223 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 202 ; 224 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 203 ; 225 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 204 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 205 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 206 ; 227 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 207 ; 228 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 208 ; 231 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 209 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 210 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 211 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 212 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 213 ; 239 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 214 ; 240 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 215 ; 241 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 216 ; 242 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 217 ; 243 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 218 ; 244 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 219 ; 245 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 220 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 221 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 222 ; 247 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 223 ; 248 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 224 ; 249 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 225 ; 250 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 226 ; 251 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 227 ; 252 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 228 ; 253 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 229 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
+; 230 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 231 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 232 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 233 ; 254 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 234 ; 255 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 235 ; 256 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 236 ; 257 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 237 ; 258 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 238 ; 259 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 239 ; 260 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 240 ; 261 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO ;
++---------------------+-------+------------------------------------+
+; I/O Standard ; Load ; Termination Resistance ;
++---------------------+-------+------------------------------------+
+; 3.3-V LVTTL ; 10 pF ; Not Available ;
+; 3.3-V LVCMOS ; 10 pF ; Not Available ;
+; 2.5 V ; 10 pF ; Not Available ;
+; 1.8 V ; 10 pF ; Not Available ;
+; 1.5 V ; 10 pF ; Not Available ;
+; SSTL-3 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-3 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; Differential SSTL-2 ; 10 pF ; (See SSTL-2) ;
+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; LVDS ; 4 pF ; 100 Ohm (Differential) ;
+; RSDS ; 10 pF ; 100 Ohm (Differential) ;
++---------------------+-------+------------------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
+; |core_top ; 398 (1) ; 141 ; 512 ; 2 ; 2 ; 0 ; 257 (1) ; 12 (0) ; 129 (0) ; 104 (0) ; 35 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 43 (42) ; 42 ; 512 ; 2 ; 0 ; 0 ; 1 (0) ; 1 (1) ; 41 (41) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 2 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
+; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
+; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
+; |execute_stage:exec_st| ; 191 (129) ; 34 ; 0 ; 0 ; 0 ; 0 ; 157 (95) ; 0 (0) ; 34 (34) ; 61 (0) ; 35 (35) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 62 (30) ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (30) ; 0 (0) ; 0 (0) ; 61 (29) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |exec_op:add_inst| ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
+; |fetch_stage:fetch_st| ; 28 (22) ; 14 ; 0 ; 0 ; 0 ; 0 ; 14 (11) ; 11 (11) ; 3 (0) ; 11 (11) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
+; |r_w_ram:instruction_ram| ; 6 (6) ; 3 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
+; |writeback_stage:writeback_st| ; 135 (28) ; 51 ; 0 ; 0 ; 0 ; 0 ; 84 (26) ; 0 (0) ; 51 (2) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
+; |extension_uart:uart| ; 107 (13) ; 49 ; 0 ; 0 ; 0 ; 0 ; 58 (3) ; 0 (0) ; 49 (10) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
+; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
++----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++----------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++---------+----------+---------------+---------------+-----------------------+-----+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
++---------+----------+---------------+---------------+-----------------------+-----+
+; bus_tx ; Output ; -- ; -- ; -- ; -- ;
+; sys_clk ; Input ; OFF ; OFF ; -- ; -- ;
++---------+----------+---------------+---------------+-----------------------+-----+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; sys_clk ; ; ;
++---------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++--------------------------------------------------------------------------------------+---------------+---------+--------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++--------------------------------------------------------------------------------------+---------------+---------+--------------+--------+----------------------+------------------+
+; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; LC_X30_Y13_N4 ; 56 ; Sync. load ; no ; -- ; -- ;
+; execute_stage:exec_st|reg.wr_en ; LC_X31_Y16_N0 ; 7 ; Write enable ; no ; -- ; -- ;
+; sys_clk ; PIN_152 ; 143 ; Clock ; yes ; Global Clock ; GCLK7 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X39_Y14_N4 ; 5 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X39_Y14_N3 ; 35 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1 ; LC_X28_Y11_N8 ; 8 ; Clock enable ; no ; -- ; -- ;
++--------------------------------------------------------------------------------------+---------------+---------+--------------+--------+----------------------+------------------+
+
+
++------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++---------+----------+---------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
++---------+----------+---------+----------------------+------------------+
+; sys_clk ; PIN_152 ; 143 ; Global Clock ; GCLK7 ;
++---------+----------+---------+----------------------+------------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals ;
++-----------------------------------------------------------------------------------+---------+
+; Name ; Fan-Out ;
++-----------------------------------------------------------------------------------+---------+
+; decode_stage:decode_st|rtw_rec.immediate[3] ; 66 ;
+; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 56 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 35 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|Equal0~10 ; 34 ;
+; execute_stage:exec_st|left_operand[28]~1 ; 32 ;
+; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
+; execute_stage:exec_st|right_operand[6]~1 ; 30 ;
+; decode_stage:decode_st|rtw_rec.rtw_reg2 ; 29 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 12 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 10 ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1 ; 8 ;
+; execute_stage:exec_st|reg.res_addr[2] ; 8 ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; 7 ;
+; execute_stage:exec_st|right_operand[6]~5 ; 7 ;
+; execute_stage:exec_st|reg.wr_en ; 7 ;
+; writeback_stage:writeback_st|wb_reg.address[0] ; 7 ;
+; writeback_stage:writeback_st|wb_reg.address[1] ; 7 ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; 6 ;
+; execute_stage:exec_st|right_operand[6]~6 ; 6 ;
+; execute_stage:exec_st|reg.result[3] ; 6 ;
+; execute_stage:exec_st|reg.result[1] ; 6 ;
+; writeback_stage:writeback_st|Equal0~24 ; 6 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 6 ;
+; ~GND ; 5 ;
+; execute_stage:exec_st|reg.result[27] ; 5 ;
+; execute_stage:exec_st|reg.result[26] ; 5 ;
+; execute_stage:exec_st|reg.result[25] ; 5 ;
+; execute_stage:exec_st|reg.result[24] ; 5 ;
+; execute_stage:exec_st|reg.result[23] ; 5 ;
+; execute_stage:exec_st|reg.result[22] ; 5 ;
+; execute_stage:exec_st|reg.result[21] ; 5 ;
+; execute_stage:exec_st|reg.result[20] ; 5 ;
+; execute_stage:exec_st|reg.result[19] ; 5 ;
+; execute_stage:exec_st|reg.result[18] ; 5 ;
+; execute_stage:exec_st|reg.result[17] ; 5 ;
+; execute_stage:exec_st|reg.result[16] ; 5 ;
+; execute_stage:exec_st|reg.result[15] ; 5 ;
+; execute_stage:exec_st|reg.result[14] ; 5 ;
+; execute_stage:exec_st|reg.result[13] ; 5 ;
+; execute_stage:exec_st|reg.result[11] ; 5 ;
+; execute_stage:exec_st|reg.result[10] ; 5 ;
+; execute_stage:exec_st|reg.result[9] ; 5 ;
+; execute_stage:exec_st|reg.result[8] ; 5 ;
+; execute_stage:exec_st|reg.result[12] ; 5 ;
+; execute_stage:exec_st|reg.result[31] ; 5 ;
+; execute_stage:exec_st|reg.result[30] ; 5 ;
+; execute_stage:exec_st|reg.result[29] ; 5 ;
+; execute_stage:exec_st|reg.result[28] ; 5 ;
+; execute_stage:exec_st|reg.result[4] ; 5 ;
+; execute_stage:exec_st|reg.result[7] ; 5 ;
++-----------------------------------------------------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary ;
++-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
+; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
++-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y16 ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y15 ;
++-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++----------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+-----------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+-----------------------+
+; C4s ; 433 / 30,600 ( 1 % ) ;
+; Direct links ; 43 / 43,552 ( < 1 % ) ;
+; Global clocks ; 1 / 8 ( 13 % ) ;
+; LAB clocks ; 12 / 312 ( 4 % ) ;
+; LUT chains ; 46 / 10,854 ( < 1 % ) ;
+; Local interconnects ; 653 / 43,552 ( 1 % ) ;
+; M4K buffers ; 64 / 1,872 ( 3 % ) ;
+; R4s ; 439 / 28,560 ( 2 % ) ;
++----------------------------+-----------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements ;
++--------------------------------------------+------------------------------+
+; Number of Logic Elements (Average = 8.29) ; Number of LABs (Total = 48) ;
++--------------------------------------------+------------------------------+
+; 1 ; 7 ;
+; 2 ; 0 ;
+; 3 ; 1 ;
+; 4 ; 1 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 2 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 37 ;
++--------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals ;
++------------------------------------+------------------------------+
+; LAB-wide Signals (Average = 0.92) ; Number of LABs (Total = 48) ;
++------------------------------------+------------------------------+
+; 1 Clock ; 39 ;
+; 1 Clock enable ; 2 ;
+; 1 Sync. load ; 2 ;
+; 2 Clock enables ; 1 ;
++------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++---------------------------------------------+------------------------------+
+; Number of Signals Sourced (Average = 9.10) ; Number of LABs (Total = 48) ;
++---------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 7 ;
+; 2 ; 0 ;
+; 3 ; 1 ;
+; 4 ; 1 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 1 ;
+; 8 ; 1 ;
+; 9 ; 0 ;
+; 10 ; 18 ;
+; 11 ; 4 ;
+; 12 ; 13 ;
+; 13 ; 1 ;
+; 14 ; 0 ;
+; 15 ; 1 ;
++---------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out (Average = 6.02) ; Number of LABs (Total = 48) ;
++-------------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 7 ;
+; 2 ; 1 ;
+; 3 ; 3 ;
+; 4 ; 3 ;
+; 5 ; 4 ;
+; 6 ; 14 ;
+; 7 ; 1 ;
+; 8 ; 1 ;
+; 9 ; 3 ;
+; 10 ; 10 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 1 ;
++-------------------------------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+------------------------------+
+; Number of Distinct Inputs (Average = 12.08) ; Number of LABs (Total = 48) ;
++----------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 7 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
+; 5 ; 1 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 2 ;
+; 9 ; 1 ;
+; 10 ; 1 ;
+; 11 ; 4 ;
+; 12 ; 0 ;
+; 13 ; 12 ;
+; 14 ; 2 ;
+; 15 ; 4 ;
+; 16 ; 0 ;
+; 17 ; 3 ;
+; 18 ; 0 ;
+; 19 ; 1 ;
+; 20 ; 3 ;
+; 21 ; 5 ;
++----------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------+
+; Fitter Device Options ;
++----------------------------------------------+---------------------+
+; Option ; Setting ;
++----------------------------------------------+---------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Active Serial ;
+; Error detection CRC ; Off ;
+; ASDO,nCSO ; As input tri-stated ;
+; Reserve all unused pins ; As input tri-stated ;
+; Base pin-out file on sameframe device ; Off ;
++----------------------------------------------+---------------------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details ;
++-----------------+----------------------+-------------------+
+; Source Register ; Destination Register ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+ Info: Processing started: Thu Dec 16 16:54:47 2010
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dt -c dt
+Info: Selected device EP1C12Q240C8 for design "dt"
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info: Device EP1C6Q240C8 is compatible
+Info: Fitter converted 2 user pins into dedicated programming pins
+ Info: Pin ~nCSO~ is reserved at location 24
+ Info: Pin ~ASDO~ is reserved at location 37
+Info: Timing-driven compilation is using the Classic Timing Analyzer
+Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
+Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Info: Completed User Assigned Global Signals Promotion Operation
+Info: DQS I/O pins require 0 global routing resources
+Info: Automatically promoted signal "sys_clk" to use Global clock in PIN 152
+Info: Completed Auto Global Promotion Operation
+Info: Starting register packing
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
+Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
+Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
+Info: Finished register packing
+Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Info: Fitter preparation operations ending: elapsed time is 00:00:01
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:01
+Info: Estimated most critical path is memory to register delay of 18.381 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y16; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3~portb_address_reg2'
+ Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y16; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3'
+ Info: 3: + IC(1.233 ns) + CELL(0.442 ns) = 5.992 ns; Loc. = LAB_X32_Y14; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[3]~61'
+ Info: 4: + IC(0.757 ns) + CELL(0.590 ns) = 7.339 ns; Loc. = LAB_X31_Y15; Fanout = 6; COMB Node = 'execute_stage:exec_st|left_operand[3]~62'
+ Info: 5: + IC(1.395 ns) + CELL(0.575 ns) = 9.309 ns; Loc. = LAB_X28_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~142COUT1_190'
+ Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 9.389 ns; Loc. = LAB_X28_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~27COUT1_192'
+ Info: 7: + IC(0.000 ns) + CELL(0.608 ns) = 9.997 ns; Loc. = LAB_X28_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~30'
+ Info: 8: + IC(1.387 ns) + CELL(0.292 ns) = 11.676 ns; Loc. = LAB_X30_Y12; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
+ Info: 9: + IC(0.900 ns) + CELL(0.442 ns) = 13.018 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~7'
+ Info: 10: + IC(0.752 ns) + CELL(0.590 ns) = 14.360 ns; Loc. = LAB_X29_Y12; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~23'
+ Info: 11: + IC(0.900 ns) + CELL(0.442 ns) = 15.702 ns; Loc. = LAB_X28_Y11; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1'
+ Info: 12: + IC(1.812 ns) + CELL(0.867 ns) = 18.381 ns; Loc. = LAB_X36_Y14; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
+ Info: Total cell delay = 9.245 ns ( 50.30 % )
+ Info: Total interconnect delay = 9.136 ns ( 49.70 % )
+Info: Fitter routing operations beginning
+Info: Router estimated average interconnect usage is 1% of the available device resources
+ Info: Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X21_Y14 to location X31_Y27
+Info: Fitter routing operations ending: elapsed time is 00:00:01
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Completed Fixed Delay Chain Operation
+Info: Started post-fitting delay annotation
+Info: Delay annotation completed successfully
+Info: Completed Auto Delay Chain Operation
+Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Info: Quartus II Fitter was successful. 0 errors, 2 warnings
+ Info: Peak virtual memory: 266 megabytes
+ Info: Processing ended: Thu Dec 16 16:54:58 2010
+ Info: Elapsed time: 00:00:11
+ Info: Total CPU time (on all processors): 00:00:11
+
+
--- /dev/null
+Fitter Status : Successful - Thu Dec 16 16:54:57 2010
+Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
+Revision Name : dt
+Top-level Entity Name : core_top
+Family : Cyclone
+Device : EP1C12Q240C8
+Timing Models : Final
+Total logic elements : 398 / 12,060 ( 3 % )
+Total pins : 2 / 173 ( 1 % )
+Total virtual pins : 0
+Total memory bits : 512 / 239,616 ( < 1 % )
+Total PLLs : 0 / 2 ( 0 % )
--- /dev/null
+Flow report for dt
+Thu Dec 16 16:55:05 2010
+Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------+
+; Flow Summary ;
++-------------------------+-----------------------------------------------+
+; Flow Status ; Successful - Thu Dec 16 16:55:05 2010 ;
+; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
+; Revision Name ; dt ;
+; Top-level Entity Name ; core_top ;
+; Family ; Cyclone ;
+; Device ; EP1C12Q240C8 ;
+; Timing Models ; Final ;
+; Met timing requirements ; Yes ;
+; Total logic elements ; 398 / 12,060 ( 3 % ) ;
+; Total pins ; 2 / 173 ( 1 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
+; Total PLLs ; 0 / 2 ( 0 % ) ;
++-------------------------+-----------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 12/16/2010 16:54:33 ;
+; Main task ; Compilation ;
+; Revision Name ; dt ;
++-------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+-----------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+-----------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 91815333562.129251487317236 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; MISC_FILE ; /homes/burban/dt/dt.dpf ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; core_top ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; core_top ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; core_top ; Top ;
+; TOP_LEVEL_ENTITY ; core_top ; dt ; -- ; -- ;
++-------------------------------------+-----------------------------+---------------+-------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:10 ; 1.0 ; -- ; 00:00:09 ;
+; Fitter ; 00:00:10 ; 1.0 ; -- ; 00:00:11 ;
+; Assembler ; 00:00:03 ; 1.0 ; -- ; 00:00:02 ;
+; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; -- ; 00:00:00 ;
+; Total ; 00:00:23 ; -- ; -- ; 00:00:22 ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++-------------------------+------------------+---------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++-------------------------+------------------+---------+------------+----------------+
+; Analysis & Synthesis ; ti9 ; Red Hat ; 5 ; x86_64 ;
+; Fitter ; ti9 ; Red Hat ; 5 ; x86_64 ;
+; Assembler ; ti9 ; Red Hat ; 5 ; x86_64 ;
+; Classic Timing Analyzer ; ti9 ; Red Hat ; 5 ; x86_64 ;
++-------------------------+------------------+---------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off dt -c dt
+quartus_fit --read_settings_files=off --write_settings_files=off dt -c dt
+quartus_asm --read_settings_files=off --write_settings_files=off dt -c dt
+quartus_tan --read_settings_files=off --write_settings_files=off dt -c dt --timing_analysis_only
+
+
+
--- /dev/null
+Analysis & Synthesis report for dt
+Thu Dec 16 16:54:44 2010
+Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Source Files Read
+ 6. Analysis & Synthesis Resource Usage Summary
+ 7. Analysis & Synthesis Resource Utilization by Entity
+ 8. Analysis & Synthesis RAM Summary
+ 9. State Machine - |core_top|decode_stage:decode_st|dec_op_inst.op_group
+ 10. Registers Removed During Synthesis
+ 11. Removed Registers Triggering Further Register Optimizations
+ 12. General Register Statistics
+ 13. Inverted Register Statistics
+ 14. Registers Packed Into Inferred Megafunctions
+ 15. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 16. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated
+ 17. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated
+ 18. Parameter Settings for User Entity Instance: fetch_stage:fetch_st
+ 19. Parameter Settings for User Entity Instance: fetch_stage:fetch_st|r_w_ram:instruction_ram
+ 20. Parameter Settings for User Entity Instance: decode_stage:decode_st
+ 21. Parameter Settings for User Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram
+ 22. Parameter Settings for User Entity Instance: execute_stage:exec_st
+ 23. Parameter Settings for User Entity Instance: execute_stage:exec_st|extension_gpm:gpmp_inst
+ 24. Parameter Settings for User Entity Instance: writeback_stage:writeback_st
+ 25. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram
+ 26. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart
+ 27. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst
+ 28. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0
+ 29. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1
+ 30. altsyncram Parameter Settings by Entity Instance
+ 31. Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart"
+ 32. Port Connectivity Checks: "writeback_stage:writeback_st"
+ 33. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
+ 34. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
+ 35. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
+ 36. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
+ 37. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
+ 38. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst"
+ 39. Port Connectivity Checks: "execute_stage:exec_st"
+ 40. Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst"
+ 41. Port Connectivity Checks: "decode_stage:decode_st"
+ 42. Port Connectivity Checks: "fetch_stage:fetch_st"
+ 43. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++-----------------------------+-----------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Thu Dec 16 16:54:44 2010 ;
+; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
+; Revision Name ; dt ;
+; Top-level Entity Name ; core_top ;
+; Family ; Cyclone ;
+; Total logic elements ; 435 ;
+; Total pins ; 2 ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 512 ;
+; Total PLLs ; 0 ;
++-----------------------------+-----------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device ; EP1C12Q240C8 ; ;
+; Top-level entity name ; core_top ; dt ;
+; Family name ; Cyclone ; Stratix II ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM Block Balancing ; On ; On ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 2 ; 2 ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Block Design Naming ; Auto ; Auto ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
+; Synthesis Seed ; 1 ; 1 ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation ;
++----------------------------+--------+
+; Processors ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 2 ;
+; Maximum allowed ; 1 ;
++----------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
+; ../cpu/src/writeback_stage_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/writeback_stage_b.vhd ;
+; ../cpu/src/writeback_stage.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/writeback_stage.vhd ;
+; ../cpu/src/rs232_tx_arc.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/rs232_tx_arc.vhd ;
+; ../cpu/src/rs232_tx.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/rs232_tx.vhd ;
+; ../cpu/src/r_w_ram_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/r_w_ram_b.vhd ;
+; ../cpu/src/r_w_ram.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/r_w_ram.vhd ;
+; ../cpu/src/r2_w_ram_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/r2_w_ram_b.vhd ;
+; ../cpu/src/r2_w_ram.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/r2_w_ram.vhd ;
+; ../cpu/src/mem_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/mem_pkg.vhd ;
+; ../cpu/src/fetch_stage_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/fetch_stage_b.vhd ;
+; ../cpu/src/fetch_stage.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/fetch_stage.vhd ;
+; ../cpu/src/extension_uart_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension_uart_pkg.vhd ;
+; ../cpu/src/extension_uart_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension_uart_b.vhd ;
+; ../cpu/src/extension_uart.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension_uart.vhd ;
+; ../cpu/src/extension_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension_pkg.vhd ;
+; ../cpu/src/extension_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension_b.vhd ;
+; ../cpu/src/extension.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension.vhd ;
+; ../cpu/src/execute_stage_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/execute_stage_b.vhd ;
+; ../cpu/src/execute_stage.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/execute_stage.vhd ;
+; ../cpu/src/exec_op.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op.vhd ;
+; ../cpu/src/decoder_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/decoder_b.vhd ;
+; ../cpu/src/decoder.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/decoder.vhd ;
+; ../cpu/src/decode_stage_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/decode_stage_b.vhd ;
+; ../cpu/src/decode_stage.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/decode_stage.vhd ;
+; ../cpu/src/core_top.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/core_top.vhd ;
+; ../cpu/src/core_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/core_pkg.vhd ;
+; ../cpu/src/common_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/common_pkg.vhd ;
+; ../cpu/src/alu_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/alu_pkg.vhd ;
+; ../cpu/src/alu_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/alu_b.vhd ;
+; ../cpu/src/alu.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/alu.vhd ;
+; ../cpu/src/exec_op/xor_op_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op/xor_op_b.vhd ;
+; ../cpu/src/exec_op/shift_op_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op/shift_op_b.vhd ;
+; ../cpu/src/exec_op/or_op_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op/or_op_b.vhd ;
+; ../cpu/src/exec_op/and_op_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op/and_op_b.vhd ;
+; ../cpu/src/exec_op/add_op_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op/add_op_b.vhd ;
+; altsyncram.tdf ; yes ; Megafunction ; /opt/altera/10.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ;
+; db/altsyncram_emk1.tdf ; yes ; Auto-Generated Megafunction ; /homes/burban/calu/dt/db/altsyncram_emk1.tdf ;
+; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /homes/burban/calu/dt/db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
++--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
+
+
++-------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+---------+
+; Resource ; Usage ;
++---------------------------------------------+---------+
+; Total logic elements ; 435 ;
+; -- Combinational with no register ; 294 ;
+; -- Register only ; 49 ;
+; -- Combinational with a register ; 92 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 105 ;
+; -- 3 input functions ; 195 ;
+; -- 2 input functions ; 80 ;
+; -- 1 input functions ; 4 ;
+; -- 0 input functions ; 2 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 335 ;
+; -- arithmetic mode ; 100 ;
+; -- qfbk mode ; 0 ;
+; -- register cascade mode ; 0 ;
+; -- synchronous clear/load mode ; 3 ;
+; -- asynchronous clear/load mode ; 0 ;
+; ; ;
+; Total registers ; 141 ;
+; Total logic cells in carry chains ; 104 ;
+; I/O pins ; 2 ;
+; Total memory bits ; 512 ;
+; Maximum fan-out node ; sys_clk ;
+; Maximum fan-out ; 205 ;
+; Total fan-out ; 1762 ;
+; Average fan-out ; 3.52 ;
++---------------------------------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
+; |core_top ; 435 (1) ; 141 ; 512 ; 2 ; 0 ; 294 (1) ; 49 (0) ; 92 (0) ; 104 (0) ; 0 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 43 (42) ; 42 ; 512 ; 0 ; 0 ; 1 (0) ; 35 (35) ; 7 (7) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
+; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
+; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
+; |execute_stage:exec_st| ; 226 (164) ; 34 ; 0 ; 0 ; 0 ; 192 (130) ; 1 (1) ; 33 (33) ; 61 (0) ; 0 (0) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 62 (30) ; 0 ; 0 ; 0 ; 0 ; 62 (30) ; 0 (0) ; 0 (0) ; 61 (29) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |exec_op:add_inst| ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
+; |fetch_stage:fetch_st| ; 29 (22) ; 14 ; 0 ; 0 ; 0 ; 15 (11) ; 12 (11) ; 2 (0) ; 11 (11) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
+; |r_w_ram:instruction_ram| ; 7 (7) ; 3 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 2 (2) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
+; |writeback_stage:writeback_st| ; 136 (28) ; 51 ; 0 ; 0 ; 0 ; 85 (26) ; 1 (0) ; 50 (2) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
+; |extension_uart:uart| ; 108 (14) ; 49 ; 0 ; 0 ; 0 ; 59 (4) ; 1 (1) ; 48 (9) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
+; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
++----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary ;
++-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------------------------+
+; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
++-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------------------------+
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
++-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------------------------+
+
+
+Encoding Type: One-Hot
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |core_top|decode_stage:decode_st|dec_op_inst.op_group ;
++--------------------------------+--------------------------------+-----------------------------+------------------------------+-------------------------------+-----------------------------+----------------------------+-----------------------------+--------------------------------+
+; Name ; dec_op_inst.op_group.JMP_ST_OP ; dec_op_inst.op_group.JMP_OP ; dec_op_inst.op_group.LDST_OP ; dec_op_inst.op_group.SHIFT_OP ; dec_op_inst.op_group.XOR_OP ; dec_op_inst.op_group.OR_OP ; dec_op_inst.op_group.AND_OP ; dec_op_inst.op_group.ADDSUB_OP ;
++--------------------------------+--------------------------------+-----------------------------+------------------------------+-------------------------------+-----------------------------+----------------------------+-----------------------------+--------------------------------+
+; dec_op_inst.op_group.ADDSUB_OP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; dec_op_inst.op_group.AND_OP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
+; dec_op_inst.op_group.OR_OP ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
+; dec_op_inst.op_group.XOR_OP ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
+; dec_op_inst.op_group.SHIFT_OP ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
+; dec_op_inst.op_group.LDST_OP ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+; dec_op_inst.op_group.JMP_OP ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+; dec_op_inst.op_group.JMP_ST_OP ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
++--------------------------------+--------------------------------+-----------------------------+------------------------------+-------------------------------+-----------------------------+----------------------------+-----------------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++--------------------------------------------------------------------------------------+------------------------------------------------------------------------+
+; Register name ; Reason for Removal ;
++--------------------------------------------------------------------------------------+------------------------------------------------------------------------+
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[24,26] ; Stuck at VCC due to stuck port data_in ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[0..2,5,8,10..14,16..18,20,22] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.prog_cnt[11..31] ; Stuck at GND due to stuck port data_in ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24,26] ; Stuck at VCC due to stuck port data_in ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0..2,5,8,10..14,16..18,20,22] ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.hword ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.byte_s ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.op_detail[1..2,5] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.brpr ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.displacement[0..2,5,8,10..31] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.saddr1[1..3] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.saddr2[1,3] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.daddr[1,3] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|reg.res_addr[1,3] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|rtw_rec.immediate[2,5,7..11,13..31] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|reg.brpr ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0] ; Lost fanout ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[29..30] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[31] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[4,6,23,25] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[3,15,19] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[7] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ;
+; decode_stage:decode_st|dec_op_inst.op_detail[0] ; Merged with decode_stage:decode_st|rtw_rec.imm_set ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29..30] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[4,6,23,25] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[3,15,19] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[7] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ;
+; decode_stage:decode_st|dec_op_inst.daddr[2] ; Lost fanout ;
+; execute_stage:exec_st|reg.res_addr[0] ; Merged with execute_stage:exec_st|reg.res_addr[2] ;
+; decode_stage:decode_st|rtw_rec.immediate[0] ; Merged with decode_stage:decode_st|rtw_rec.immediate[12] ;
+; decode_stage:decode_st|rtw_rec.immediate[4] ; Merged with decode_stage:decode_st|rtw_rec.immediate[6] ;
+; decode_stage:decode_st|rtw_rec.immediate[1] ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
+; decode_stage:decode_st|dec_op_inst.condition[1..2] ; Merged with decode_stage:decode_st|dec_op_inst.condition[3] ;
+; decode_stage:decode_st|dec_op_inst.displacement[7] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[9] ;
+; decode_stage:decode_st|dec_op_inst.displacement[4] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[6] ;
+; decode_stage:decode_st|dec_op_inst.saddr2[0] ; Merged with decode_stage:decode_st|dec_op_inst.saddr2[2] ;
+; decode_stage:decode_st|dec_op_inst.op_detail[4] ; Stuck at VCC due to stuck port data_in ;
+; execute_stage:exec_st|reg.alu_jump ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.condition[0] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|rtw_rec.imm_set ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
+; decode_stage:decode_st|dec_op_inst.displacement[6] ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
+; decode_stage:decode_st|dec_op_inst.op_detail[3] ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
+; writeback_stage:writeback_st|wb_reg.dmem_write_en ; Merged with writeback_stage:writeback_st|wb_reg.dmem_en ;
+; decode_stage:decode_st|dec_op_inst.saddr1[0] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[3] ;
+; decode_stage:decode_st|dec_op_inst.prog_cnt[0..10] ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.condition[3] ; Lost fanout ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31] ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; Lost fanout ;
+; fetch_stage:fetch_st|instr_r_addr[11..31] ; Lost fanout ;
+; Total Number of Removed Registers = 330 ; ;
++--------------------------------------------------------------------------------------+------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations ;
++-----------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------+
+; Register name ; Reason for Removal ; Registers Removed due to This Register ;
++-----------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------+
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[28] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.brpr, execute_stage:exec_st|reg.brpr, ;
+; ; due to stuck port data_in ; execute_stage:exec_st|reg.alu_jump, ;
+; ; ; decode_stage:decode_st|dec_op_inst.condition[0], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry, ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0], ;
+; ; ; decode_stage:decode_st|dec_op_inst.condition[3], ;
+; ; ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.op_detail[5], ;
+; ; due to stuck port data_in ; decode_stage:decode_st|dec_op_inst.op_detail[1], ;
+; ; ; decode_stage:decode_st|dec_op_inst.saddr1[3], ;
+; ; ; decode_stage:decode_st|dec_op_inst.saddr1[1], ;
+; ; ; decode_stage:decode_st|dec_op_inst.saddr2[3], ;
+; ; ; decode_stage:decode_st|dec_op_inst.saddr2[1], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[31], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[26], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[25], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[24], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[23], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[22], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[21], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[20], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[19], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[18], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[17], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[16], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[15], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[14], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[13], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[11], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[10], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[9], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[8], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[7], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[5], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[2], ;
+; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[8], ;
+; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[9], ;
+; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[10], ;
+; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[2], ;
+; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[5], ;
+; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[7] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[1] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.op_detail[2], ;
+; ; due to stuck port data_in ; decode_stage:decode_st|dec_op_inst.displacement[1], ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[22] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[3], execute_stage:exec_st|reg.res_addr[3] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[20] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[1], execute_stage:exec_st|reg.res_addr[1] ;
+; ; due to stuck port data_in ; ;
+; decode_stage:decode_st|dec_op_inst.prog_cnt[31] ; Stuck at GND ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ;
+; ; due to stuck port data_in ; ;
+; decode_stage:decode_st|dec_op_inst.prog_cnt[23] ; Stuck at GND ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[14] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[14] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[13] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[13] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[12] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[12] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[11] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[11] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[10] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[10] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[8] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[8] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[5] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[5] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[2] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[2] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[0] ;
+; ; due to stuck port data_in ; ;
++-----------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 141 ;
+; Number of registers using Synchronous Clear ; 1 ;
+; Number of registers using Synchronous Load ; 2 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 13 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++------------------------------------------------------------------------------------------------+
+; Inverted Register Statistics ;
++--------------------------------------------------------------------------------------+---------+
+; Inverted Register ; Fan out ;
++--------------------------------------------------------------------------------------+---------+
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 1 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[21] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[20] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[19] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 2 ;
+; Total number of inverted registers = 12 ; ;
++--------------------------------------------------------------------------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Registers Packed Into Inferred Megafunctions ;
++------------------------------------------------------------+-----------------------------------------------------+------+
+; Register Name ; Megafunction ; Type ;
++------------------------------------------------------------+-----------------------------------------------------+------+
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
++------------------------------------------------------------+-----------------------------------------------------+------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
+; 3:1 ; 21 bits ; 42 LEs ; 21 LEs ; 21 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[24] ;
+; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[12] ;
+; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ;
+; 18:1 ; 3 bits ; 36 LEs ; 3 LEs ; 33 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ;
+; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22] ;
+; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |core_top|writeback_stage:writeback_st|ext_uart.addr[1] ;
+; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|left_operand[28] ;
+; 4:1 ; 28 bits ; 56 LEs ; 56 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[2] ;
+; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[6] ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ;
++---------------------------------+--------------------+------+-----------------------------------------------------------+
+; Assignment ; Value ; From ; To ;
++---------------------------------+--------------------+------+-----------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
++---------------------------------+--------------------+------+-----------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ;
++---------------------------------+--------------------+------+-----------------------------------------------------------+
+; Assignment ; Value ; From ; To ;
++---------------------------------+--------------------+------+-----------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
++---------------------------------+--------------------+------+-----------------------------------------------------------+
+
+
++-------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: fetch_stage:fetch_st ;
++----------------+-------+------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+------------------------------------------+
+; reset_value ; '0' ; Enumerated ;
+; logic_act ; '1' ; Enumerated ;
++----------------+-------+------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: fetch_stage:fetch_st|r_w_ram:instruction_ram ;
++----------------+-------+------------------------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+------------------------------------------------------------------+
+; addr_width ; 11 ; Signed Integer ;
+; data_width ; 32 ; Signed Integer ;
++----------------+-------+------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: decode_stage:decode_st ;
++----------------+-------+--------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------------------+
+; reset_value ; '0' ; Enumerated ;
+; logic_act ; '1' ; Enumerated ;
++----------------+-------+--------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram ;
++----------------+-------+------------------------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+------------------------------------------------------------------+
+; addr_width ; 4 ; Signed Integer ;
+; data_width ; 32 ; Signed Integer ;
++----------------+-------+------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: execute_stage:exec_st ;
++----------------+-------+-------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+-------------------------------------------+
+; reset_value ; '0' ; Enumerated ;
++----------------+-------+-------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: execute_stage:exec_st|extension_gpm:gpmp_inst ;
++----------------+-------+-------------------------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+-------------------------------------------------------------------+
+; reset_value ; '0' ; Enumerated ;
++----------------+-------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: writeback_stage:writeback_st ;
++----------------+-------+--------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------------------------+
+; reset_value ; '0' ; Enumerated ;
+; logic_act ; '1' ; Enumerated ;
++----------------+-------+--------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram ;
++----------------+-------+-------------------------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+-------------------------------------------------------------------+
+; addr_width ; 11 ; Signed Integer ;
+; data_width ; 32 ; Signed Integer ;
++----------------+-------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart ;
++----------------+-------+----------------------------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+----------------------------------------------------------------------+
+; reset_value ; '0' ; Enumerated ;
++----------------+-------+----------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ;
++----------------+-------+---------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+---------------------------------------------------------------------------------------------+
+; reset_value ; '0' ; Enumerated ;
++----------------+-------+---------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ;
++------------------------------------+--------------------------------------+----------------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------------------------+--------------------------------------+----------------------------------------+
+; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+; WIDTH_BYTEENA ; 1 ; Untyped ;
+; OPERATION_MODE ; DUAL_PORT ; Untyped ;
+; WIDTH_A ; 32 ; Untyped ;
+; WIDTHAD_A ; 4 ; Untyped ;
+; NUMWORDS_A ; 16 ; Untyped ;
+; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
+; ADDRESS_ACLR_A ; NONE ; Untyped ;
+; OUTDATA_ACLR_A ; NONE ; Untyped ;
+; WRCONTROL_ACLR_A ; NONE ; Untyped ;
+; INDATA_ACLR_A ; NONE ; Untyped ;
+; BYTEENA_ACLR_A ; NONE ; Untyped ;
+; WIDTH_B ; 32 ; Untyped ;
+; WIDTHAD_B ; 4 ; Untyped ;
+; NUMWORDS_B ; 16 ; Untyped ;
+; INDATA_REG_B ; CLOCK1 ; Untyped ;
+; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
+; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
+; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
+; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
+; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
+; INDATA_ACLR_B ; NONE ; Untyped ;
+; WRCONTROL_ACLR_B ; NONE ; Untyped ;
+; ADDRESS_ACLR_B ; NONE ; Untyped ;
+; OUTDATA_ACLR_B ; NONE ; Untyped ;
+; RDCONTROL_ACLR_B ; NONE ; Untyped ;
+; BYTEENA_ACLR_B ; NONE ; Untyped ;
+; WIDTH_BYTEENA_A ; 1 ; Untyped ;
+; WIDTH_BYTEENA_B ; 1 ; Untyped ;
+; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
+; BYTE_SIZE ; 8 ; Untyped ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
+; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
+; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
+; INIT_FILE ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; Untyped ;
+; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
+; MAXIMUM_DEPTH ; 0 ; Untyped ;
+; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
+; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
+; ENABLE_ECC ; FALSE ; Untyped ;
+; DEVICE_FAMILY ; Cyclone ; Untyped ;
+; CBXI_PARAMETER ; altsyncram_emk1 ; Untyped ;
++------------------------------------+--------------------------------------+----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
++------------------------------------+--------------------------------------+----------------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------------------------+--------------------------------------+----------------------------------------+
+; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+; WIDTH_BYTEENA ; 1 ; Untyped ;
+; OPERATION_MODE ; DUAL_PORT ; Untyped ;
+; WIDTH_A ; 32 ; Untyped ;
+; WIDTHAD_A ; 4 ; Untyped ;
+; NUMWORDS_A ; 16 ; Untyped ;
+; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
+; ADDRESS_ACLR_A ; NONE ; Untyped ;
+; OUTDATA_ACLR_A ; NONE ; Untyped ;
+; WRCONTROL_ACLR_A ; NONE ; Untyped ;
+; INDATA_ACLR_A ; NONE ; Untyped ;
+; BYTEENA_ACLR_A ; NONE ; Untyped ;
+; WIDTH_B ; 32 ; Untyped ;
+; WIDTHAD_B ; 4 ; Untyped ;
+; NUMWORDS_B ; 16 ; Untyped ;
+; INDATA_REG_B ; CLOCK1 ; Untyped ;
+; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
+; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
+; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
+; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
+; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
+; INDATA_ACLR_B ; NONE ; Untyped ;
+; WRCONTROL_ACLR_B ; NONE ; Untyped ;
+; ADDRESS_ACLR_B ; NONE ; Untyped ;
+; OUTDATA_ACLR_B ; NONE ; Untyped ;
+; RDCONTROL_ACLR_B ; NONE ; Untyped ;
+; BYTEENA_ACLR_B ; NONE ; Untyped ;
+; WIDTH_BYTEENA_A ; 1 ; Untyped ;
+; WIDTH_BYTEENA_B ; 1 ; Untyped ;
+; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
+; BYTE_SIZE ; 8 ; Untyped ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
+; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
+; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
+; INIT_FILE ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; Untyped ;
+; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
+; MAXIMUM_DEPTH ; 0 ; Untyped ;
+; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
+; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
+; ENABLE_ECC ; FALSE ; Untyped ;
+; DEVICE_FAMILY ; Cyclone ; Untyped ;
+; CBXI_PARAMETER ; altsyncram_emk1 ; Untyped ;
++------------------------------------+--------------------------------------+----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------+
+; altsyncram Parameter Settings by Entity Instance ;
++-------------------------------------------+-------------------------------------------------------------------+
+; Name ; Value ;
++-------------------------------------------+-------------------------------------------------------------------+
+; Number of entity instances ; 2 ;
+; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ;
+; -- OPERATION_MODE ; DUAL_PORT ;
+; -- WIDTH_A ; 32 ;
+; -- NUMWORDS_A ; 16 ;
+; -- OUTDATA_REG_A ; UNREGISTERED ;
+; -- WIDTH_B ; 32 ;
+; -- NUMWORDS_B ; 16 ;
+; -- ADDRESS_REG_B ; CLOCK0 ;
+; -- OUTDATA_REG_B ; UNREGISTERED ;
+; -- RAM_BLOCK_TYPE ; AUTO ;
+; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
+; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
+; -- OPERATION_MODE ; DUAL_PORT ;
+; -- WIDTH_A ; 32 ;
+; -- NUMWORDS_A ; 16 ;
+; -- OUTDATA_REG_A ; UNREGISTERED ;
+; -- WIDTH_B ; 32 ;
+; -- NUMWORDS_B ; 16 ;
+; -- ADDRESS_REG_B ; CLOCK0 ;
+; -- OUTDATA_REG_B ; UNREGISTERED ;
+; -- RAM_BLOCK_TYPE ; AUTO ;
+; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
++-------------------------------------------+-------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart" ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; data_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------+
+; Port Connectivity Checks: "writeback_stage:writeback_st" ;
++-------+-------+----------+-------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+-------------------------------+
+; reset ; Input ; Info ; Stuck at VCC ;
++-------+-------+----------+-------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst" ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+; alu_result.status.zero ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.status.sign ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.alu_jump ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.brpr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.reg_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.mem_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.mem_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst" ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+; alu_result.status.zero ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.status.sign ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.alu_jump ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.brpr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.reg_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.mem_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.mem_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst" ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+; alu_result.status.zero ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.status.sign ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.alu_jump ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.brpr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.reg_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.mem_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.mem_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst" ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+; alu_result.status.zero ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.status.sign ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.alu_jump ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.brpr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.reg_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.mem_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.mem_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst" ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+; alu_result.status.zero ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.status.sign ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.alu_jump ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.brpr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.reg_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.mem_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; alu_result.mem_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------------------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst" ;
++--------------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++--------------------+--------+----------+-------------------------------------------------------------------------------------+
+; alu_state.reg_op ; Input ; Info ; Stuck at GND ;
+; alu_state.mem_op ; Input ; Info ; Stuck at GND ;
+; alu_state.mem_en ; Input ; Info ; Stuck at GND ;
+; alu_state.hw_op ; Input ; Info ; Stuck at GND ;
+; alu_state.byte_op ; Input ; Info ; Stuck at GND ;
+; alu_state.sign_xt ; Input ; Info ; Stuck at GND ;
+; alu_result.sign_xt ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++--------------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "execute_stage:exec_st" ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+; reset ; Input ; Info ; Stuck at VCC ;
+; ext_data_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst" ;
++--------------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++--------------------+--------+----------+-------------------------------------------------------------------------------------+
+; instr_spl.jmptype ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; instr_spl.high_low ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; instr_spl.fill ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; instr_spl.signext ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++--------------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------+
+; Port Connectivity Checks: "decode_stage:decode_st" ;
++-------+-------+----------+-------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+-------------------------+
+; reset ; Input ; Info ; Stuck at VCC ;
++-------+-------+----------+-------------------------+
+
+
++--------------------------------------------------+
+; Port Connectivity Checks: "fetch_stage:fetch_st" ;
++-------+-------+----------+-----------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+-----------------------+
+; reset ; Input ; Info ; Stuck at VCC ;
++-------+-------+----------+-----------------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+ Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+ Info: Processing started: Thu Dec 16 16:54:33 2010
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dt -c dt
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/writeback_stage_b.vhd
+ Info: Found design unit 1: writeback_stage-behav
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/writeback_stage.vhd
+ Info: Found entity 1: writeback_stage
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/rw_r_ram_b.vhd
+ Info: Found design unit 1: rw_r_ram-behaviour
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/rw_r_ram.vhd
+ Info: Found entity 1: rw_r_ram
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/rs232_tx_arc.vhd
+ Info: Found design unit 1: rs232_tx-beh
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/rs232_tx.vhd
+ Info: Found entity 1: rs232_tx
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/r_w_ram_b.vhd
+ Info: Found design unit 1: r_w_ram-behaviour
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/r_w_ram.vhd
+ Info: Found entity 1: r_w_ram
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/r2_w_ram_b.vhd
+ Info: Found design unit 1: r2_w_ram-behaviour
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/r2_w_ram.vhd
+ Info: Found entity 1: r2_w_ram
+Info: Found 3 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/pipeline_tb.vhd
+ Info: Found design unit 1: pipeline_tb-behavior
+ Info: Found design unit 2: pipeline_conf_beh
+ Info: Found entity 1: pipeline_tb
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/mem_pkg.vhd
+ Info: Found design unit 1: mem_pkg
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/fetch_stage_b.vhd
+ Info: Found design unit 1: fetch_stage-behav
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/fetch_stage.vhd
+ Info: Found entity 1: fetch_stage
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/extension_uart_pkg.vhd
+ Info: Found design unit 1: extension_uart_pkg
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/extension_uart_b.vhd
+ Info: Found design unit 1: extension_uart-behav
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/extension_uart.vhd
+ Info: Found entity 1: extension_uart
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/extension_pkg.vhd
+ Info: Found design unit 1: extension_pkg
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/extension_b.vhd
+ Info: Found design unit 1: extension_gpm-behav
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/extension.vhd
+ Info: Found entity 1: extension_gpm
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/execute_stage_b.vhd
+ Info: Found design unit 1: execute_stage-behav
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/execute_stage.vhd
+ Info: Found entity 1: execute_stage
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/exec_op.vhd
+ Info: Found entity 1: exec_op
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/decoder_b.vhd
+ Info: Found design unit 1: decoder-behav_d
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/decoder.vhd
+ Info: Found entity 1: decoder
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/decode_stage_b.vhd
+ Info: Found design unit 1: decode_stage-behav
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/decode_stage.vhd
+ Info: Found entity 1: decode_stage
+Info: Found 2 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/core_top.vhd
+ Info: Found design unit 1: core_top-behav
+ Info: Found entity 1: core_top
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/core_pkg.vhd
+ Info: Found design unit 1: core_pkg
+Info: Found 2 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/common_pkg.vhd
+ Info: Found design unit 1: common_pkg
+ Info: Found design unit 2: common_pkg-body
+Info: Found 2 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/alu_pkg.vhd
+ Info: Found design unit 1: alu_pkg
+ Info: Found design unit 2: alu_pkg-body
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/alu_b.vhd
+ Info: Found design unit 1: alu-behaviour
+Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/alu.vhd
+ Info: Found entity 1: alu
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/exec_op/xor_op_b.vhd
+ Info: Found design unit 1: exec_op-xor_op
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/exec_op/shift_op_b.vhd
+ Info: Found design unit 1: exec_op-shift_op
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/exec_op/or_op_b.vhd
+ Info: Found design unit 1: exec_op-or_op
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/exec_op/and_op_b.vhd
+ Info: Found design unit 1: exec_op-and_op
+Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/exec_op/add_op_b.vhd
+ Info: Found design unit 1: exec_op-add_op
+Info: Elaborating entity "core_top" for the top level hierarchy
+Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(24): object "jump_result" assigned a value but never read
+Warning (10541): VHDL Signal Declaration warning at core_top.vhd(53): used implicit default value for signal "gpm_in_pin" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(54): object "gpm_out_pin" assigned a value but never read
+Info: Elaborating entity "fetch_stage" for hierarchy "fetch_stage:fetch_st"
+Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(11): used implicit default value for signal "instr_w_addr" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(14): used implicit default value for signal "instr_we" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(15): used implicit default value for signal "instr_wr_data" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Info: Elaborating entity "r_w_ram" for hierarchy "fetch_stage:fetch_st|r_w_ram:instruction_ram"
+Warning (10036): Verilog HDL or VHDL warning at r_w_ram_b.vhd(15): object "ram" assigned a value but never read
+Info: Elaborating entity "decode_stage" for hierarchy "decode_stage:decode_st"
+Info: Elaborating entity "r2_w_ram" for hierarchy "decode_stage:decode_st|r2_w_ram:register_ram"
+Info: Elaborating entity "decoder" for hierarchy "decode_stage:decode_st|decoder:decoder_inst"
+Info: Elaborating entity "execute_stage" for hierarchy "execute_stage:exec_st"
+Warning (10541): VHDL Signal Declaration warning at execute_stage_b.vhd(19): used implicit default value for signal "ext_gpmp" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Info: Elaborating entity "alu" for hierarchy "execute_stage:exec_st|alu:alu_inst"
+Info: Elaborating entity "exec_op" using architecture "A:add_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
+Info: Elaborating entity "exec_op" using architecture "A:and_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
+Info: Elaborating entity "exec_op" using architecture "A:or_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
+Info: Elaborating entity "exec_op" using architecture "A:xor_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
+Info: Elaborating entity "exec_op" using architecture "A:shift_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
+Info: Elaborating entity "extension_gpm" for hierarchy "execute_stage:exec_st|extension_gpm:gpmp_inst"
+Info: Elaborating entity "writeback_stage" for hierarchy "writeback_stage:writeback_st"
+Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(14): object "data_ram_read_ext" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(18): object "ext_timer" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(18): object "ext_gpmp" assigned a value but never read
+Warning (10812): VHDL warning at writeback_stage_b.vhd(152): sensitivity list already contains wb_reg_nxt
+Info: Elaborating entity "extension_uart" for hierarchy "writeback_stage:writeback_st|extension_uart:uart"
+Info: Elaborating entity "rs232_tx" for hierarchy "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst"
+Info: Inferred 2 megafunctions from design logic
+ Info: Inferred altsyncram megafunction from the following design logic: "decode_stage:decode_st|r2_w_ram:register_ram|ram~37"
+ Info: Parameter OPERATION_MODE set to DUAL_PORT
+ Info: Parameter WIDTH_A set to 32
+ Info: Parameter WIDTHAD_A set to 4
+ Info: Parameter NUMWORDS_A set to 16
+ Info: Parameter WIDTH_B set to 32
+ Info: Parameter WIDTHAD_B set to 4
+ Info: Parameter NUMWORDS_B set to 16
+ Info: Parameter ADDRESS_ACLR_A set to NONE
+ Info: Parameter OUTDATA_REG_B set to UNREGISTERED
+ Info: Parameter ADDRESS_ACLR_B set to NONE
+ Info: Parameter OUTDATA_ACLR_B set to NONE
+ Info: Parameter ADDRESS_REG_B set to CLOCK0
+ Info: Parameter INDATA_ACLR_A set to NONE
+ Info: Parameter WRCONTROL_ACLR_A set to NONE
+ Info: Parameter INIT_FILE set to db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif
+ Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
+ Info: Inferred altsyncram megafunction from the following design logic: "decode_stage:decode_st|r2_w_ram:register_ram|ram~38"
+ Info: Parameter OPERATION_MODE set to DUAL_PORT
+ Info: Parameter WIDTH_A set to 32
+ Info: Parameter WIDTHAD_A set to 4
+ Info: Parameter NUMWORDS_A set to 16
+ Info: Parameter WIDTH_B set to 32
+ Info: Parameter WIDTHAD_B set to 4
+ Info: Parameter NUMWORDS_B set to 16
+ Info: Parameter ADDRESS_ACLR_A set to NONE
+ Info: Parameter OUTDATA_REG_B set to UNREGISTERED
+ Info: Parameter ADDRESS_ACLR_B set to NONE
+ Info: Parameter OUTDATA_ACLR_B set to NONE
+ Info: Parameter ADDRESS_REG_B set to CLOCK0
+ Info: Parameter INDATA_ACLR_A set to NONE
+ Info: Parameter WRCONTROL_ACLR_A set to NONE
+ Info: Parameter INIT_FILE set to db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif
+ Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
+Info: Elaborated megafunction instantiation "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0"
+Info: Instantiated megafunction "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0" with the following parameter:
+ Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
+ Info: Parameter "WIDTH_A" = "32"
+ Info: Parameter "WIDTHAD_A" = "4"
+ Info: Parameter "NUMWORDS_A" = "16"
+ Info: Parameter "WIDTH_B" = "32"
+ Info: Parameter "WIDTHAD_B" = "4"
+ Info: Parameter "NUMWORDS_B" = "16"
+ Info: Parameter "ADDRESS_ACLR_A" = "NONE"
+ Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
+ Info: Parameter "ADDRESS_ACLR_B" = "NONE"
+ Info: Parameter "OUTDATA_ACLR_B" = "NONE"
+ Info: Parameter "ADDRESS_REG_B" = "CLOCK0"
+ Info: Parameter "INDATA_ACLR_A" = "NONE"
+ Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
+ Info: Parameter "INIT_FILE" = "db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif"
+ Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_emk1.tdf
+ Info: Found entity 1: altsyncram_emk1
+Info: Elaborated megafunction instantiation "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1"
+Info: Instantiated megafunction "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1" with the following parameter:
+ Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
+ Info: Parameter "WIDTH_A" = "32"
+ Info: Parameter "WIDTHAD_A" = "4"
+ Info: Parameter "NUMWORDS_A" = "16"
+ Info: Parameter "WIDTH_B" = "32"
+ Info: Parameter "WIDTHAD_B" = "4"
+ Info: Parameter "NUMWORDS_B" = "16"
+ Info: Parameter "ADDRESS_ACLR_A" = "NONE"
+ Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
+ Info: Parameter "ADDRESS_ACLR_B" = "NONE"
+ Info: Parameter "OUTDATA_ACLR_B" = "NONE"
+ Info: Parameter "ADDRESS_REG_B" = "CLOCK0"
+ Info: Parameter "INDATA_ACLR_A" = "NONE"
+ Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
+ Info: Parameter "INIT_FILE" = "db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif"
+ Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
+Info: 132 registers lost all their fanouts during netlist optimizations. The first 132 are displayed below.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1]" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.daddr[2]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[8]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[9]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[10]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[0]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[1]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[2]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[3]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[4]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[5]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[6]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[7]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.condition[3]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31]" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.op_group.AND_OP" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.op_group.OR_OP" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.op_group.XOR_OP" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.op_group.JMP_OP" lost all its fanouts during netlist optimizations.
+ Info: Register "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[31]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[30]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[29]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[28]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[27]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[26]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[25]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[24]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[23]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[22]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[21]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[20]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[19]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[18]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[17]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[16]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[15]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[14]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[13]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[12]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[11]" lost all its fanouts during netlist optimizations.
+Info: Removed 1 MSB VCC or GND address nodes from RAM block "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM"
+Info: Removed 1 MSB VCC or GND address nodes from RAM block "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM"
+Info: Generating hard_block partition "hard_block:auto_generated_inst"
+Info: Implemented 501 device resources after synthesis - the final resource count might be different
+ Info: Implemented 1 input pins
+ Info: Implemented 1 output pins
+ Info: Implemented 435 logic cells
+ Info: Implemented 64 RAM segments
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
+ Info: Peak virtual memory: 267 megabytes
+ Info: Processing ended: Thu Dec 16 16:54:44 2010
+ Info: Elapsed time: 00:00:11
+ Info: Total CPU time (on all processors): 00:00:10
+
+
--- /dev/null
+Analysis & Synthesis Status : Successful - Thu Dec 16 16:54:44 2010
+Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
+Revision Name : dt
+Top-level Entity Name : core_top
+Family : Cyclone
+Total logic elements : 435
+Total pins : 2
+Total virtual pins : 0
+Total memory bits : 512
+Total PLLs : 0
--- /dev/null
+ -- Copyright (C) 1991-2010 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+CHIP "dt" ASSIGNED TO AN: EP1C12Q240C8
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+RESERVED_INPUT : 1 : : : : 1 :
+RESERVED_INPUT : 2 : : : : 1 :
+RESERVED_INPUT : 3 : : : : 1 :
+RESERVED_INPUT : 4 : : : : 1 :
+RESERVED_INPUT : 5 : : : : 1 :
+RESERVED_INPUT : 6 : : : : 1 :
+RESERVED_INPUT : 7 : : : : 1 :
+RESERVED_INPUT : 8 : : : : 1 :
+VCCIO1 : 9 : power : : 3.3V : 1 :
+GND : 10 : gnd : : : :
+RESERVED_INPUT : 11 : : : : 1 :
+RESERVED_INPUT : 12 : : : : 1 :
+RESERVED_INPUT : 13 : : : : 1 :
+RESERVED_INPUT : 14 : : : : 1 :
+RESERVED_INPUT : 15 : : : : 1 :
+RESERVED_INPUT : 16 : : : : 1 :
+RESERVED_INPUT : 17 : : : : 1 :
+RESERVED_INPUT : 18 : : : : 1 :
+RESERVED_INPUT : 19 : : : : 1 :
+RESERVED_INPUT : 20 : : : : 1 :
+RESERVED_INPUT : 21 : : : : 1 :
+VCCIO1 : 22 : power : : 3.3V : 1 :
+RESERVED_INPUT : 23 : : : : 1 :
+~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 24 : input : 3.3-V LVCMOS : : 1 : N
+DATA0 : 25 : input : : : 1 :
+nCONFIG : 26 : : : : 1 :
+VCCA_PLL1 : 27 : power : : 1.5V : :
+GND+ : 28 : : : : 1 :
+GND+ : 29 : : : : 1 :
+GNDA_PLL1 : 30 : gnd : : : :
+GNDG_PLL1 : 31 : gnd : : : :
+nCEO : 32 : : : : 1 :
+nCE : 33 : : : : 1 :
+MSEL0 : 34 : : : : 1 :
+MSEL1 : 35 : : : : 1 :
+DCLK : 36 : bidir : : : 1 :
+~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 37 : input : 3.3-V LVCMOS : : 1 : N
+RESERVED_INPUT : 38 : : : : 1 :
+RESERVED_INPUT : 39 : : : : 1 :
+GND : 40 : gnd : : : :
+RESERVED_INPUT : 41 : : : : 1 :
+RESERVED_INPUT : 42 : : : : 1 :
+RESERVED_INPUT : 43 : : : : 1 :
+RESERVED_INPUT : 44 : : : : 1 :
+RESERVED_INPUT : 45 : : : : 1 :
+RESERVED_INPUT : 46 : : : : 1 :
+RESERVED_INPUT : 47 : : : : 1 :
+RESERVED_INPUT : 48 : : : : 1 :
+RESERVED_INPUT : 49 : : : : 1 :
+RESERVED_INPUT : 50 : : : : 1 :
+VCCIO1 : 51 : power : : 3.3V : 1 :
+GND : 52 : gnd : : : :
+RESERVED_INPUT : 53 : : : : 1 :
+RESERVED_INPUT : 54 : : : : 1 :
+RESERVED_INPUT : 55 : : : : 1 :
+RESERVED_INPUT : 56 : : : : 1 :
+RESERVED_INPUT : 57 : : : : 1 :
+RESERVED_INPUT : 58 : : : : 1 :
+RESERVED_INPUT : 59 : : : : 1 :
+RESERVED_INPUT : 60 : : : : 1 :
+RESERVED_INPUT : 61 : : : : 4 :
+RESERVED_INPUT : 62 : : : : 4 :
+RESERVED_INPUT : 63 : : : : 4 :
+RESERVED_INPUT : 64 : : : : 4 :
+RESERVED_INPUT : 65 : : : : 4 :
+RESERVED_INPUT : 66 : : : : 4 :
+RESERVED_INPUT : 67 : : : : 4 :
+RESERVED_INPUT : 68 : : : : 4 :
+GND : 69 : gnd : : : :
+VCCIO4 : 70 : power : : 3.3V : 4 :
+GND : 71 : gnd : : : :
+VCCINT : 72 : power : : 1.5V : :
+RESERVED_INPUT : 73 : : : : 4 :
+RESERVED_INPUT : 74 : : : : 4 :
+RESERVED_INPUT : 75 : : : : 4 :
+RESERVED_INPUT : 76 : : : : 4 :
+RESERVED_INPUT : 77 : : : : 4 :
+RESERVED_INPUT : 78 : : : : 4 :
+RESERVED_INPUT : 79 : : : : 4 :
+GND : 80 : gnd : : : :
+VCCINT : 81 : power : : 1.5V : :
+RESERVED_INPUT : 82 : : : : 4 :
+RESERVED_INPUT : 83 : : : : 4 :
+RESERVED_INPUT : 84 : : : : 4 :
+RESERVED_INPUT : 85 : : : : 4 :
+RESERVED_INPUT : 86 : : : : 4 :
+RESERVED_INPUT : 87 : : : : 4 :
+RESERVED_INPUT : 88 : : : : 4 :
+GND : 89 : gnd : : : :
+VCCINT : 90 : power : : 1.5V : :
+GND : 91 : gnd : : : :
+VCCIO4 : 92 : power : : 3.3V : 4 :
+RESERVED_INPUT : 93 : : : : 4 :
+RESERVED_INPUT : 94 : : : : 4 :
+RESERVED_INPUT : 95 : : : : 4 :
+GND : 96 : gnd : : : :
+VCCINT : 97 : power : : 1.5V : :
+RESERVED_INPUT : 98 : : : : 4 :
+RESERVED_INPUT : 99 : : : : 4 :
+RESERVED_INPUT : 100 : : : : 4 :
+RESERVED_INPUT : 101 : : : : 4 :
+GND : 102 : gnd : : : :
+VCCINT : 103 : power : : 1.5V : :
+RESERVED_INPUT : 104 : : : : 4 :
+RESERVED_INPUT : 105 : : : : 4 :
+RESERVED_INPUT : 106 : : : : 4 :
+RESERVED_INPUT : 107 : : : : 4 :
+RESERVED_INPUT : 108 : : : : 4 :
+GND : 109 : gnd : : : :
+VCCINT : 110 : power : : 1.5V : :
+GND : 111 : gnd : : : :
+VCCIO4 : 112 : power : : 3.3V : 4 :
+RESERVED_INPUT : 113 : : : : 4 :
+RESERVED_INPUT : 114 : : : : 4 :
+RESERVED_INPUT : 115 : : : : 4 :
+RESERVED_INPUT : 116 : : : : 4 :
+RESERVED_INPUT : 117 : : : : 4 :
+RESERVED_INPUT : 118 : : : : 4 :
+RESERVED_INPUT : 119 : : : : 4 :
+RESERVED_INPUT : 120 : : : : 4 :
+RESERVED_INPUT : 121 : : : : 3 :
+RESERVED_INPUT : 122 : : : : 3 :
+RESERVED_INPUT : 123 : : : : 3 :
+RESERVED_INPUT : 124 : : : : 3 :
+RESERVED_INPUT : 125 : : : : 3 :
+RESERVED_INPUT : 126 : : : : 3 :
+RESERVED_INPUT : 127 : : : : 3 :
+RESERVED_INPUT : 128 : : : : 3 :
+GND : 129 : gnd : : : :
+VCCIO3 : 130 : power : : 3.3V : 3 :
+RESERVED_INPUT : 131 : : : : 3 :
+RESERVED_INPUT : 132 : : : : 3 :
+RESERVED_INPUT : 133 : : : : 3 :
+RESERVED_INPUT : 134 : : : : 3 :
+RESERVED_INPUT : 135 : : : : 3 :
+RESERVED_INPUT : 136 : : : : 3 :
+RESERVED_INPUT : 137 : : : : 3 :
+RESERVED_INPUT : 138 : : : : 3 :
+RESERVED_INPUT : 139 : : : : 3 :
+RESERVED_INPUT : 140 : : : : 3 :
+RESERVED_INPUT : 141 : : : : 3 :
+GND : 142 : gnd : : : :
+RESERVED_INPUT : 143 : : : : 3 :
+RESERVED_INPUT : 144 : : : : 3 :
+CONF_DONE : 145 : : : : 3 :
+nSTATUS : 146 : : : : 3 :
+TCK : 147 : input : : : 3 :
+TMS : 148 : input : : : 3 :
+TDO : 149 : output : : : 3 :
+GNDG_PLL2 : 150 : gnd : : : :
+GNDA_PLL2 : 151 : gnd : : : :
+sys_clk : 152 : input : 3.3-V LVCMOS : : 3 : Y
+GND+ : 153 : : : : 3 :
+VCCA_PLL2 : 154 : power : : 1.5V : :
+TDI : 155 : input : : : 3 :
+RESERVED_INPUT : 156 : : : : 3 :
+VCCIO3 : 157 : power : : 3.3V : 3 :
+RESERVED_INPUT : 158 : : : : 3 :
+RESERVED_INPUT : 159 : : : : 3 :
+RESERVED_INPUT : 160 : : : : 3 :
+RESERVED_INPUT : 161 : : : : 3 :
+RESERVED_INPUT : 162 : : : : 3 :
+RESERVED_INPUT : 163 : : : : 3 :
+RESERVED_INPUT : 164 : : : : 3 :
+RESERVED_INPUT : 165 : : : : 3 :
+bus_tx : 166 : output : 3.3-V LVCMOS : : 3 : Y
+RESERVED_INPUT : 167 : : : : 3 :
+RESERVED_INPUT : 168 : : : : 3 :
+RESERVED_INPUT : 169 : : : : 3 :
+RESERVED_INPUT : 170 : : : : 3 :
+GND : 171 : gnd : : : :
+VCCIO3 : 172 : power : : 3.3V : 3 :
+RESERVED_INPUT : 173 : : : : 3 :
+RESERVED_INPUT : 174 : : : : 3 :
+RESERVED_INPUT : 175 : : : : 3 :
+RESERVED_INPUT : 176 : : : : 3 :
+RESERVED_INPUT : 177 : : : : 3 :
+RESERVED_INPUT : 178 : : : : 3 :
+RESERVED_INPUT : 179 : : : : 3 :
+RESERVED_INPUT : 180 : : : : 3 :
+RESERVED_INPUT : 181 : : : : 2 :
+RESERVED_INPUT : 182 : : : : 2 :
+RESERVED_INPUT : 183 : : : : 2 :
+RESERVED_INPUT : 184 : : : : 2 :
+RESERVED_INPUT : 185 : : : : 2 :
+RESERVED_INPUT : 186 : : : : 2 :
+RESERVED_INPUT : 187 : : : : 2 :
+RESERVED_INPUT : 188 : : : : 2 :
+VCCIO2 : 189 : power : : 3.3V : 2 :
+GND : 190 : gnd : : : :
+VCCINT : 191 : power : : 1.5V : :
+GND : 192 : gnd : : : :
+RESERVED_INPUT : 193 : : : : 2 :
+RESERVED_INPUT : 194 : : : : 2 :
+RESERVED_INPUT : 195 : : : : 2 :
+RESERVED_INPUT : 196 : : : : 2 :
+RESERVED_INPUT : 197 : : : : 2 :
+VCCINT : 198 : power : : 1.5V : :
+GND : 199 : gnd : : : :
+RESERVED_INPUT : 200 : : : : 2 :
+RESERVED_INPUT : 201 : : : : 2 :
+RESERVED_INPUT : 202 : : : : 2 :
+RESERVED_INPUT : 203 : : : : 2 :
+VCCINT : 204 : power : : 1.5V : :
+GND : 205 : gnd : : : :
+RESERVED_INPUT : 206 : : : : 2 :
+RESERVED_INPUT : 207 : : : : 2 :
+RESERVED_INPUT : 208 : : : : 2 :
+VCCIO2 : 209 : power : : 3.3V : 2 :
+GND : 210 : gnd : : : :
+VCCINT : 211 : power : : 1.5V : :
+GND : 212 : gnd : : : :
+RESERVED_INPUT : 213 : : : : 2 :
+RESERVED_INPUT : 214 : : : : 2 :
+RESERVED_INPUT : 215 : : : : 2 :
+RESERVED_INPUT : 216 : : : : 2 :
+RESERVED_INPUT : 217 : : : : 2 :
+RESERVED_INPUT : 218 : : : : 2 :
+RESERVED_INPUT : 219 : : : : 2 :
+VCCINT : 220 : power : : 1.5V : :
+GND : 221 : gnd : : : :
+RESERVED_INPUT : 222 : : : : 2 :
+RESERVED_INPUT : 223 : : : : 2 :
+RESERVED_INPUT : 224 : : : : 2 :
+RESERVED_INPUT : 225 : : : : 2 :
+RESERVED_INPUT : 226 : : : : 2 :
+RESERVED_INPUT : 227 : : : : 2 :
+RESERVED_INPUT : 228 : : : : 2 :
+VCCINT : 229 : power : : 1.5V : :
+GND : 230 : gnd : : : :
+VCCIO2 : 231 : power : : 3.3V : 2 :
+GND : 232 : gnd : : : :
+RESERVED_INPUT : 233 : : : : 2 :
+RESERVED_INPUT : 234 : : : : 2 :
+RESERVED_INPUT : 235 : : : : 2 :
+RESERVED_INPUT : 236 : : : : 2 :
+RESERVED_INPUT : 237 : : : : 2 :
+RESERVED_INPUT : 238 : : : : 2 :
+RESERVED_INPUT : 239 : : : : 2 :
+RESERVED_INPUT : 240 : : : : 2 :
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+# Date created = 15:08:54 December 16, 2010
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "10.0"
+DATE = "15:08:54 December 16, 2010"
+
+# Revisions
+
+PROJECT_REVISION = "dt"
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+# Date created = 15:08:54 December 16, 2010
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# dt_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name DEVICE EP1C12Q240C8
+set_global_assignment -name TOP_LEVEL_ENTITY core_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:08:54 DECEMBER 16, 2010"
+set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx_arc.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/pipeline_tb.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/mem_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decoder_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decoder.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/core_top.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/core_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/common_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/alu_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/alu_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/alu.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/xor_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name MISC_FILE /homes/burban/dt/dt.dpf
+set_location_assignment PIN_166 -to bus_tx
+set_location_assignment PIN_152 -to sys_clk
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
--- /dev/null
+Classic Timing Analyzer report for dt
+Thu Dec 16 16:55:05 2010
+Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Classic Timing Analyzer Deprecation
+ 3. Timing Analyzer Summary
+ 4. Timing Analyzer Settings
+ 5. Clock Settings Summary
+ 6. Parallel Compilation
+ 7. Clock Setup: 'sys_clk'
+ 8. tco
+ 9. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
+---------------------------------------
+; Classic Timing Analyzer Deprecation ;
+---------------------------------------
+Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
++------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
+; Worst-case tco ; N/A ; None ; 8.846 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ;
+; Clock Setup: 'sys_clk' ; N/A ; None ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; 0 ;
+; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
++------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Settings ;
++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
+; Option ; Setting ; From ; To ; Entity Name ;
++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
+; Device Name ; EP1C12Q240C8 ; ; ; ;
+; Timing Models ; Final ; ; ; ;
+; Default hold multicycle ; Same as Multicycle ; ; ; ;
+; Cut paths between unrelated clock domains ; On ; ; ; ;
+; Cut off read during write signal paths ; On ; ; ; ;
+; Cut off feedback from I/O pins ; On ; ; ; ;
+; Report Combined Fast/Slow Timing ; Off ; ; ; ;
+; Ignore Clock Settings ; Off ; ; ; ;
+; Analyze latches as synchronous elements ; On ; ; ; ;
+; Enable Recovery/Removal analysis ; Off ; ; ; ;
+; Enable Clock Latency ; Off ; ; ; ;
+; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+; Minimum Core Junction Temperature ; 0 ; ; ; ;
+; Maximum Core Junction Temperature ; 85 ; ; ; ;
+; Number of source nodes to report per destination node ; 10 ; ; ; ;
+; Number of destination nodes to report ; 10 ; ; ; ;
+; Number of paths to report ; 200 ; ; ; ;
+; Report Minimum Timing Checks ; Off ; ; ; ;
+; Use Fast Timing Models ; Off ; ; ; ;
+; Report IO Paths Separately ; Off ; ; ; ;
+; Perform Multicorner Analysis ; Off ; ; ; ;
+; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ;
+; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ;
+; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Settings Summary ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+; sys_clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation ;
++----------------------------+--------+
+; Processors ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 2 ;
+; Maximum allowed ; 1 ;
++----------------------------+--------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'sys_clk' ;
++-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
+; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
+; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
+; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
+; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
+; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
+; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
+; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
+; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
+; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
+; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
+; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
+; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ;
+; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ;
+; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
+; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ;
+; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ;
+; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
+; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ;
+; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ;
+; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ;
+; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ;
+; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ;
+; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ;
+; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ;
+; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ;
+; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ;
+; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ;
+; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ;
+; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ;
+; N/A ; 59.51 MHz ( period = 16.805 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.544 ns ;
+; N/A ; 59.51 MHz ( period = 16.805 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.544 ns ;
+; N/A ; 59.73 MHz ( period = 16.743 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.473 ns ;
+; N/A ; 59.73 MHz ( period = 16.743 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.473 ns ;
+; N/A ; 60.26 MHz ( period = 16.594 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.324 ns ;
+; N/A ; 60.26 MHz ( period = 16.594 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.324 ns ;
+; N/A ; 60.70 MHz ( period = 16.475 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.205 ns ;
+; N/A ; 60.70 MHz ( period = 16.475 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.205 ns ;
+; N/A ; 61.33 MHz ( period = 16.306 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.036 ns ;
+; N/A ; 61.33 MHz ( period = 16.306 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.036 ns ;
+; N/A ; 62.02 MHz ( period = 16.125 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.797 ns ;
+; N/A ; 62.17 MHz ( period = 16.085 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.815 ns ;
+; N/A ; 62.17 MHz ( period = 16.085 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.815 ns ;
+; N/A ; 62.25 MHz ( period = 16.063 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.726 ns ;
+; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
+; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
+; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
+; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
+; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
+; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
+; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
+; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
+; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
+; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
+; N/A ; 62.84 MHz ( period = 15.914 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.577 ns ;
+; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
+; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
+; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
+; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
+; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
+; N/A ; 63.24 MHz ( period = 15.812 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.542 ns ;
+; N/A ; 63.24 MHz ( period = 15.812 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.542 ns ;
+; N/A ; 63.31 MHz ( period = 15.795 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.458 ns ;
+; N/A ; 63.53 MHz ( period = 15.741 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.480 ns ;
+; N/A ; 63.53 MHz ( period = 15.741 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.480 ns ;
+; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
+; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
+; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
+; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
+; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
+; N/A ; 64.00 MHz ( period = 15.626 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.289 ns ;
+; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
+; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
+; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
+; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
+; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
+; N/A ; 64.86 MHz ( period = 15.417 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.156 ns ;
+; N/A ; 64.86 MHz ( period = 15.417 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.156 ns ;
+; N/A ; 64.91 MHz ( period = 15.405 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.068 ns ;
+; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
+; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
+; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
+; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
+; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
+; N/A ; 66.09 MHz ( period = 15.132 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.795 ns ;
+; N/A ; 66.12 MHz ( period = 15.123 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.862 ns ;
+; N/A ; 66.40 MHz ( period = 15.061 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.733 ns ;
+; N/A ; 66.40 MHz ( period = 15.061 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.791 ns ;
+; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
+; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
+; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
+; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
+; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
+; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
+; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
+; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
+; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
+; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
+; N/A ; 67.06 MHz ( period = 14.912 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.642 ns ;
+; N/A ; 67.32 MHz ( period = 14.854 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.593 ns ;
+; N/A ; 67.32 MHz ( period = 14.854 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.593 ns ;
+; N/A ; 67.60 MHz ( period = 14.793 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.523 ns ;
+; N/A ; 67.86 MHz ( period = 14.737 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.409 ns ;
+; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
+; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
+; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
+; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
+; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
+; N/A ; 68.38 MHz ( period = 14.624 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.354 ns ;
+; N/A ; 68.41 MHz ( period = 14.618 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.424 ns ;
+; N/A ; 68.41 MHz ( period = 14.618 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.424 ns ;
+; N/A ; 68.73 MHz ( period = 14.549 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.288 ns ;
+; N/A ; 68.73 MHz ( period = 14.549 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.288 ns ;
+; N/A ; 68.77 MHz ( period = 14.541 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.280 ns ;
+; N/A ; 68.77 MHz ( period = 14.541 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.280 ns ;
+; N/A ; 69.24 MHz ( period = 14.443 ns ) ; decode_stage:decode_st|rtw_rec.immediate[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.182 ns ;
+; N/A ; 69.24 MHz ( period = 14.443 ns ) ; decode_stage:decode_st|rtw_rec.immediate[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.182 ns ;
+; N/A ; 69.43 MHz ( period = 14.403 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.133 ns ;
+; N/A ; 69.48 MHz ( period = 14.393 ns ) ; execute_stage:exec_st|reg.result[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.132 ns ;
+; N/A ; 69.48 MHz ( period = 14.393 ns ) ; execute_stage:exec_st|reg.result[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.132 ns ;
+; N/A ; 69.59 MHz ( period = 14.369 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.108 ns ;
+; N/A ; 69.59 MHz ( period = 14.369 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.108 ns ;
+; N/A ; 70.14 MHz ( period = 14.258 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.997 ns ;
+; N/A ; 70.14 MHz ( period = 14.258 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.997 ns ;
+; N/A ; 70.48 MHz ( period = 14.189 ns ) ; execute_stage:exec_st|reg.result[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.928 ns ;
+; N/A ; 70.48 MHz ( period = 14.189 ns ) ; execute_stage:exec_st|reg.result[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.928 ns ;
+; N/A ; 70.55 MHz ( period = 14.175 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.905 ns ;
+; N/A ; 70.55 MHz ( period = 14.175 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.905 ns ;
+; N/A ; 70.55 MHz ( period = 14.174 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.846 ns ;
+; N/A ; 70.64 MHz ( period = 14.156 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.828 ns ;
+; N/A ; 70.77 MHz ( period = 14.130 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 13.860 ns ;
+; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
+; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
+; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
+; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
+; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
+; N/A ; 70.95 MHz ( period = 14.094 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.757 ns ;
+; N/A ; 71.06 MHz ( period = 14.072 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[5] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.811 ns ;
+; N/A ; 71.06 MHz ( period = 14.072 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[5] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.811 ns ;
+; N/A ; 71.13 MHz ( period = 14.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 13.798 ns ;
+; N/A ; 71.71 MHz ( period = 13.945 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.608 ns ;
+; N/A ; 71.73 MHz ( period = 13.942 ns ) ; decode_stage:decode_st|rtw_rec.immediate[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.681 ns ;
+; N/A ; 71.73 MHz ( period = 13.942 ns ) ; decode_stage:decode_st|rtw_rec.immediate[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.681 ns ;
+; N/A ; 71.75 MHz ( period = 13.938 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.677 ns ;
+; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ;
+; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ;
+; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ;
+; N/A ; 72.07 MHz ( period = 13.875 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[10] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.614 ns ;
+; N/A ; 72.07 MHz ( period = 13.875 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[10] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.614 ns ;
+; N/A ; 72.10 MHz ( period = 13.869 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.541 ns ;
+; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
+; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
+; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
+; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
+; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
+; N/A ; 72.14 MHz ( period = 13.861 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.533 ns ;
+; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ;
+; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ;
+; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ;
+; N/A ; 72.33 MHz ( period = 13.826 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.489 ns ;
+; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ;
+; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ;
+; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ;
+; N/A ; 72.47 MHz ( period = 13.799 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[13] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.529 ns ;
+; N/A ; 72.47 MHz ( period = 13.799 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[13] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.529 ns ;
+; N/A ; 72.48 MHz ( period = 13.796 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 13.093 ns ;
+; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
+; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
+; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
+; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
++-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; tco ;
++-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
+; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
++-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
+; N/A ; None ; 8.846 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ;
++-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Classic Timing Analyzer
+ Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+ Info: Processing started: Thu Dec 16 16:55:05 2010
+Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dt -c dt --timing_analysis_only
+Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
+Warning: Found pins functioning as undefined clocks and/or memory enables
+ Info: Assuming node "sys_clk" is an undefined clock
+Info: Clock "sys_clk" has Internal fmax of 49.7 MHz between source memory "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0" and destination register "writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]" (period= 20.119 ns)
+ Info: + Longest memory to register delay is 19.416 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y16; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
+ Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y16; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a9'
+ Info: 3: + IC(1.893 ns) + CELL(0.114 ns) = 6.324 ns; Loc. = LC_X27_Y12_N5; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[9]~23'
+ Info: 4: + IC(0.416 ns) + CELL(0.114 ns) = 6.854 ns; Loc. = LC_X27_Y12_N2; Fanout = 6; COMB Node = 'execute_stage:exec_st|left_operand[9]~24'
+ Info: 5: + IC(1.990 ns) + CELL(0.564 ns) = 9.408 ns; Loc. = LC_X28_Y13_N3; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~52'
+ Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 9.586 ns; Loc. = LC_X28_Y13_N4; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~57'
+ Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 9.794 ns; Loc. = LC_X28_Y13_N9; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~77'
+ Info: 8: + IC(0.000 ns) + CELL(0.679 ns) = 10.473 ns; Loc. = LC_X28_Y12_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~90'
+ Info: 9: + IC(1.498 ns) + CELL(0.114 ns) = 12.085 ns; Loc. = LC_X32_Y12_N1; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~14'
+ Info: 10: + IC(0.428 ns) + CELL(0.590 ns) = 13.103 ns; Loc. = LC_X32_Y12_N2; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~17'
+ Info: 11: + IC(1.142 ns) + CELL(0.590 ns) = 14.835 ns; Loc. = LC_X29_Y12_N8; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~23'
+ Info: 12: + IC(1.556 ns) + CELL(0.114 ns) = 16.505 ns; Loc. = LC_X28_Y11_N8; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1'
+ Info: 13: + IC(2.044 ns) + CELL(0.867 ns) = 19.416 ns; Loc. = LC_X36_Y14_N5; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
+ Info: Total cell delay = 8.449 ns ( 43.52 % )
+ Info: Total interconnect delay = 10.967 ns ( 56.48 % )
+ Info: - Smallest clock skew is -0.016 ns
+ Info: + Shortest clock path from clock "sys_clk" to destination register is 3.178 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk'
+ Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X36_Y14_N5; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
+ Info: Total cell delay = 2.180 ns ( 68.60 % )
+ Info: Total interconnect delay = 0.998 ns ( 31.40 % )
+ Info: - Longest clock path from clock "sys_clk" to source memory is 3.194 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk'
+ Info: 2: + IC(1.007 ns) + CELL(0.718 ns) = 3.194 ns; Loc. = M4K_X33_Y16; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
+ Info: Total cell delay = 2.187 ns ( 68.47 % )
+ Info: Total interconnect delay = 1.007 ns ( 31.53 % )
+ Info: + Micro clock to output delay of source is 0.650 ns
+ Info: + Micro setup delay of destination is 0.037 ns
+Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 8.846 ns
+ Info: + Longest clock path from clock "sys_clk" to source register is 3.178 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk'
+ Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X36_Y14_N2; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
+ Info: Total cell delay = 2.180 ns ( 68.60 % )
+ Info: Total interconnect delay = 0.998 ns ( 31.40 % )
+ Info: + Micro clock to output delay of source is 0.224 ns
+ Info: + Longest register to pin delay is 5.444 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y14_N2; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
+ Info: 2: + IC(3.320 ns) + CELL(2.124 ns) = 5.444 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx'
+ Info: Total cell delay = 2.124 ns ( 39.02 % )
+ Info: Total interconnect delay = 3.320 ns ( 60.98 % )
+Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
+ Info: Peak virtual memory: 187 megabytes
+ Info: Processing ended: Thu Dec 16 16:55:06 2010
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
+
+
--- /dev/null
+--------------------------------------------------------------------------------------
+Timing Analyzer Summary
+--------------------------------------------------------------------------------------
+
+Type : Worst-case tco
+Slack : N/A
+Required Time : None
+Actual Time : 8.846 ns
+From : writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int
+To : bus_tx
+From Clock : sys_clk
+To Clock : --
+Failed Paths : 0
+
+Type : Clock Setup: 'sys_clk'
+Slack : N/A
+Required Time : None
+Actual Time : 49.70 MHz ( period = 20.119 ns )
+From : decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2
+To : writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4]
+From Clock : sys_clk
+To Clock : sys_clk
+Failed Paths : 0
+
+Type : Total number of failed paths
+Slack :
+Required Time :
+Actual Time :
+From :
+To :
+From Clock :
+To Clock :
+Failed Paths : 0
+
+--------------------------------------------------------------------------------------
+
projects / calu.git / commitdiff