1 Classic Timing Analyzer report for dt
2 Thu Dec 16 16:55:05 2010
3 Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
10 2. Classic Timing Analyzer Deprecation
11 3. Timing Analyzer Summary
12 4. Timing Analyzer Settings
13 5. Clock Settings Summary
14 6. Parallel Compilation
15 7. Clock Setup: 'sys_clk'
17 9. Timing Analyzer Messages
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40 ---------------------------------------
41 ; Classic Timing Analyzer Deprecation ;
42 ---------------------------------------
43 Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
46 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
47 ; Timing Analyzer Summary ;
48 +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
49 ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
50 +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
51 ; Worst-case tco ; N/A ; None ; 8.846 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ;
52 ; Clock Setup: 'sys_clk' ; N/A ; None ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; 0 ;
53 ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
54 +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
57 +-----------------------------------------------------------------------------------------------------------------------------------------------------+
58 ; Timing Analyzer Settings ;
59 +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
60 ; Option ; Setting ; From ; To ; Entity Name ;
61 +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
62 ; Device Name ; EP1C12Q240C8 ; ; ; ;
63 ; Timing Models ; Final ; ; ; ;
64 ; Default hold multicycle ; Same as Multicycle ; ; ; ;
65 ; Cut paths between unrelated clock domains ; On ; ; ; ;
66 ; Cut off read during write signal paths ; On ; ; ; ;
67 ; Cut off feedback from I/O pins ; On ; ; ; ;
68 ; Report Combined Fast/Slow Timing ; Off ; ; ; ;
69 ; Ignore Clock Settings ; Off ; ; ; ;
70 ; Analyze latches as synchronous elements ; On ; ; ; ;
71 ; Enable Recovery/Removal analysis ; Off ; ; ; ;
72 ; Enable Clock Latency ; Off ; ; ; ;
73 ; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
74 ; Minimum Core Junction Temperature ; 0 ; ; ; ;
75 ; Maximum Core Junction Temperature ; 85 ; ; ; ;
76 ; Number of source nodes to report per destination node ; 10 ; ; ; ;
77 ; Number of destination nodes to report ; 10 ; ; ; ;
78 ; Number of paths to report ; 200 ; ; ; ;
79 ; Report Minimum Timing Checks ; Off ; ; ; ;
80 ; Use Fast Timing Models ; Off ; ; ; ;
81 ; Report IO Paths Separately ; Off ; ; ; ;
82 ; Perform Multicorner Analysis ; Off ; ; ; ;
83 ; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
84 ; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ;
85 ; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ;
86 ; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
87 +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
90 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
91 ; Clock Settings Summary ;
92 +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
93 ; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
94 +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
95 ; sys_clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
96 +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
99 Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
100 +-------------------------------------+
101 ; Parallel Compilation ;
102 +----------------------------+--------+
103 ; Processors ; Number ;
104 +----------------------------+--------+
105 ; Number detected on machine ; 2 ;
106 ; Maximum allowed ; 1 ;
107 +----------------------------+--------+
110 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
111 ; Clock Setup: 'sys_clk' ;
112 +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
113 ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
114 +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
115 ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
116 ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
117 ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
118 ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
119 ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
120 ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
121 ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
122 ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
123 ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
124 ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
125 ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
126 ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
127 ; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ;
128 ; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ;
129 ; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ;
130 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
131 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
132 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
133 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
134 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
135 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
136 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
137 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
138 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
139 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
140 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
141 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
142 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
143 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
144 ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
145 ; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ;
146 ; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ;
147 ; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ;
148 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
149 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
150 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
151 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
152 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
153 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
154 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
155 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
156 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
157 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
158 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
159 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
160 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
161 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
162 ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
163 ; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ;
164 ; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ;
165 ; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ;
166 ; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ;
167 ; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ;
168 ; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ;
169 ; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ;
170 ; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ;
171 ; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ;
172 ; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ;
173 ; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ;
174 ; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ;
175 ; N/A ; 59.51 MHz ( period = 16.805 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.544 ns ;
176 ; N/A ; 59.51 MHz ( period = 16.805 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.544 ns ;
177 ; N/A ; 59.73 MHz ( period = 16.743 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.473 ns ;
178 ; N/A ; 59.73 MHz ( period = 16.743 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.473 ns ;
179 ; N/A ; 60.26 MHz ( period = 16.594 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.324 ns ;
180 ; N/A ; 60.26 MHz ( period = 16.594 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.324 ns ;
181 ; N/A ; 60.70 MHz ( period = 16.475 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.205 ns ;
182 ; N/A ; 60.70 MHz ( period = 16.475 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.205 ns ;
183 ; N/A ; 61.33 MHz ( period = 16.306 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.036 ns ;
184 ; N/A ; 61.33 MHz ( period = 16.306 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.036 ns ;
185 ; N/A ; 62.02 MHz ( period = 16.125 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.797 ns ;
186 ; N/A ; 62.17 MHz ( period = 16.085 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.815 ns ;
187 ; N/A ; 62.17 MHz ( period = 16.085 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.815 ns ;
188 ; N/A ; 62.25 MHz ( period = 16.063 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.726 ns ;
189 ; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
190 ; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
191 ; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
192 ; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
193 ; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
194 ; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
195 ; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
196 ; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
197 ; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
198 ; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
199 ; N/A ; 62.84 MHz ( period = 15.914 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.577 ns ;
200 ; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
201 ; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
202 ; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
203 ; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
204 ; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
205 ; N/A ; 63.24 MHz ( period = 15.812 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.542 ns ;
206 ; N/A ; 63.24 MHz ( period = 15.812 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.542 ns ;
207 ; N/A ; 63.31 MHz ( period = 15.795 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.458 ns ;
208 ; N/A ; 63.53 MHz ( period = 15.741 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.480 ns ;
209 ; N/A ; 63.53 MHz ( period = 15.741 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.480 ns ;
210 ; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
211 ; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
212 ; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
213 ; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
214 ; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
215 ; N/A ; 64.00 MHz ( period = 15.626 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.289 ns ;
216 ; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
217 ; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
218 ; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
219 ; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
220 ; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
221 ; N/A ; 64.86 MHz ( period = 15.417 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.156 ns ;
222 ; N/A ; 64.86 MHz ( period = 15.417 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.156 ns ;
223 ; N/A ; 64.91 MHz ( period = 15.405 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.068 ns ;
224 ; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
225 ; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
226 ; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
227 ; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
228 ; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
229 ; N/A ; 66.09 MHz ( period = 15.132 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.795 ns ;
230 ; N/A ; 66.12 MHz ( period = 15.123 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.862 ns ;
231 ; N/A ; 66.40 MHz ( period = 15.061 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.733 ns ;
232 ; N/A ; 66.40 MHz ( period = 15.061 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.791 ns ;
233 ; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
234 ; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
235 ; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
236 ; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
237 ; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
238 ; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
239 ; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
240 ; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
241 ; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
242 ; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
243 ; N/A ; 67.06 MHz ( period = 14.912 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.642 ns ;
244 ; N/A ; 67.32 MHz ( period = 14.854 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.593 ns ;
245 ; N/A ; 67.32 MHz ( period = 14.854 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.593 ns ;
246 ; N/A ; 67.60 MHz ( period = 14.793 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.523 ns ;
247 ; N/A ; 67.86 MHz ( period = 14.737 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.409 ns ;
248 ; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
249 ; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
250 ; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
251 ; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
252 ; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
253 ; N/A ; 68.38 MHz ( period = 14.624 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.354 ns ;
254 ; N/A ; 68.41 MHz ( period = 14.618 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.424 ns ;
255 ; N/A ; 68.41 MHz ( period = 14.618 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.424 ns ;
256 ; N/A ; 68.73 MHz ( period = 14.549 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.288 ns ;
257 ; N/A ; 68.73 MHz ( period = 14.549 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.288 ns ;
258 ; N/A ; 68.77 MHz ( period = 14.541 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.280 ns ;
259 ; N/A ; 68.77 MHz ( period = 14.541 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.280 ns ;
260 ; N/A ; 69.24 MHz ( period = 14.443 ns ) ; decode_stage:decode_st|rtw_rec.immediate[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.182 ns ;
261 ; N/A ; 69.24 MHz ( period = 14.443 ns ) ; decode_stage:decode_st|rtw_rec.immediate[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.182 ns ;
262 ; N/A ; 69.43 MHz ( period = 14.403 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.133 ns ;
263 ; N/A ; 69.48 MHz ( period = 14.393 ns ) ; execute_stage:exec_st|reg.result[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.132 ns ;
264 ; N/A ; 69.48 MHz ( period = 14.393 ns ) ; execute_stage:exec_st|reg.result[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.132 ns ;
265 ; N/A ; 69.59 MHz ( period = 14.369 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.108 ns ;
266 ; N/A ; 69.59 MHz ( period = 14.369 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.108 ns ;
267 ; N/A ; 70.14 MHz ( period = 14.258 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.997 ns ;
268 ; N/A ; 70.14 MHz ( period = 14.258 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.997 ns ;
269 ; N/A ; 70.48 MHz ( period = 14.189 ns ) ; execute_stage:exec_st|reg.result[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.928 ns ;
270 ; N/A ; 70.48 MHz ( period = 14.189 ns ) ; execute_stage:exec_st|reg.result[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.928 ns ;
271 ; N/A ; 70.55 MHz ( period = 14.175 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.905 ns ;
272 ; N/A ; 70.55 MHz ( period = 14.175 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.905 ns ;
273 ; N/A ; 70.55 MHz ( period = 14.174 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.846 ns ;
274 ; N/A ; 70.64 MHz ( period = 14.156 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.828 ns ;
275 ; N/A ; 70.77 MHz ( period = 14.130 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 13.860 ns ;
276 ; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
277 ; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
278 ; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
279 ; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
280 ; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
281 ; N/A ; 70.95 MHz ( period = 14.094 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.757 ns ;
282 ; N/A ; 71.06 MHz ( period = 14.072 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[5] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.811 ns ;
283 ; N/A ; 71.06 MHz ( period = 14.072 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[5] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.811 ns ;
284 ; N/A ; 71.13 MHz ( period = 14.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 13.798 ns ;
285 ; N/A ; 71.71 MHz ( period = 13.945 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.608 ns ;
286 ; N/A ; 71.73 MHz ( period = 13.942 ns ) ; decode_stage:decode_st|rtw_rec.immediate[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.681 ns ;
287 ; N/A ; 71.73 MHz ( period = 13.942 ns ) ; decode_stage:decode_st|rtw_rec.immediate[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.681 ns ;
288 ; N/A ; 71.75 MHz ( period = 13.938 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.677 ns ;
289 ; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ;
290 ; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ;
291 ; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ;
292 ; N/A ; 72.07 MHz ( period = 13.875 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[10] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.614 ns ;
293 ; N/A ; 72.07 MHz ( period = 13.875 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[10] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.614 ns ;
294 ; N/A ; 72.10 MHz ( period = 13.869 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.541 ns ;
295 ; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
296 ; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
297 ; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
298 ; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
299 ; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
300 ; N/A ; 72.14 MHz ( period = 13.861 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.533 ns ;
301 ; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ;
302 ; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ;
303 ; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ;
304 ; N/A ; 72.33 MHz ( period = 13.826 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.489 ns ;
305 ; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ;
306 ; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ;
307 ; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ;
308 ; N/A ; 72.47 MHz ( period = 13.799 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[13] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.529 ns ;
309 ; N/A ; 72.47 MHz ( period = 13.799 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[13] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.529 ns ;
310 ; N/A ; 72.48 MHz ( period = 13.796 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 13.093 ns ;
311 ; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
312 ; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
313 ; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
314 ; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
315 ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
316 +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
319 +----------------------------------------------------------------------------------------------------------------------------------------------+
321 +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
322 ; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
323 +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
324 ; N/A ; None ; 8.846 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ;
325 +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
328 +--------------------------+
329 ; Timing Analyzer Messages ;
330 +--------------------------+
331 Info: *******************************************************************
332 Info: Running Quartus II Classic Timing Analyzer
333 Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
334 Info: Processing started: Thu Dec 16 16:55:05 2010
335 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dt -c dt --timing_analysis_only
336 Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
337 Warning: Found pins functioning as undefined clocks and/or memory enables
338 Info: Assuming node "sys_clk" is an undefined clock
339 Info: Clock "sys_clk" has Internal fmax of 49.7 MHz between source memory "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0" and destination register "writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]" (period= 20.119 ns)
340 Info: + Longest memory to register delay is 19.416 ns
341 Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y16; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
342 Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y16; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a9'
343 Info: 3: + IC(1.893 ns) + CELL(0.114 ns) = 6.324 ns; Loc. = LC_X27_Y12_N5; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[9]~23'
344 Info: 4: + IC(0.416 ns) + CELL(0.114 ns) = 6.854 ns; Loc. = LC_X27_Y12_N2; Fanout = 6; COMB Node = 'execute_stage:exec_st|left_operand[9]~24'
345 Info: 5: + IC(1.990 ns) + CELL(0.564 ns) = 9.408 ns; Loc. = LC_X28_Y13_N3; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~52'
346 Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 9.586 ns; Loc. = LC_X28_Y13_N4; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~57'
347 Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 9.794 ns; Loc. = LC_X28_Y13_N9; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~77'
348 Info: 8: + IC(0.000 ns) + CELL(0.679 ns) = 10.473 ns; Loc. = LC_X28_Y12_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~90'
349 Info: 9: + IC(1.498 ns) + CELL(0.114 ns) = 12.085 ns; Loc. = LC_X32_Y12_N1; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~14'
350 Info: 10: + IC(0.428 ns) + CELL(0.590 ns) = 13.103 ns; Loc. = LC_X32_Y12_N2; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~17'
351 Info: 11: + IC(1.142 ns) + CELL(0.590 ns) = 14.835 ns; Loc. = LC_X29_Y12_N8; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~23'
352 Info: 12: + IC(1.556 ns) + CELL(0.114 ns) = 16.505 ns; Loc. = LC_X28_Y11_N8; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1'
353 Info: 13: + IC(2.044 ns) + CELL(0.867 ns) = 19.416 ns; Loc. = LC_X36_Y14_N5; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
354 Info: Total cell delay = 8.449 ns ( 43.52 % )
355 Info: Total interconnect delay = 10.967 ns ( 56.48 % )
356 Info: - Smallest clock skew is -0.016 ns
357 Info: + Shortest clock path from clock "sys_clk" to destination register is 3.178 ns
358 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk'
359 Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X36_Y14_N5; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
360 Info: Total cell delay = 2.180 ns ( 68.60 % )
361 Info: Total interconnect delay = 0.998 ns ( 31.40 % )
362 Info: - Longest clock path from clock "sys_clk" to source memory is 3.194 ns
363 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk'
364 Info: 2: + IC(1.007 ns) + CELL(0.718 ns) = 3.194 ns; Loc. = M4K_X33_Y16; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
365 Info: Total cell delay = 2.187 ns ( 68.47 % )
366 Info: Total interconnect delay = 1.007 ns ( 31.53 % )
367 Info: + Micro clock to output delay of source is 0.650 ns
368 Info: + Micro setup delay of destination is 0.037 ns
369 Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 8.846 ns
370 Info: + Longest clock path from clock "sys_clk" to source register is 3.178 ns
371 Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk'
372 Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X36_Y14_N2; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
373 Info: Total cell delay = 2.180 ns ( 68.60 % )
374 Info: Total interconnect delay = 0.998 ns ( 31.40 % )
375 Info: + Micro clock to output delay of source is 0.224 ns
376 Info: + Longest register to pin delay is 5.444 ns
377 Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y14_N2; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
378 Info: 2: + IC(3.320 ns) + CELL(2.124 ns) = 5.444 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx'
379 Info: Total cell delay = 2.124 ns ( 39.02 % )
380 Info: Total interconnect delay = 3.320 ns ( 60.98 % )
381 Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
382 Info: Peak virtual memory: 187 megabytes
383 Info: Processing ended: Thu Dec 16 16:55:06 2010
384 Info: Elapsed time: 00:00:01
385 Info: Total CPU time (on all processors): 00:00:01
projects / calu.git / blob