Cristian Magherusan-Stanciu [Mon, 16 May 2011 01:35:03 +0000 (01:35 +0000)]
Add crossgcc target to automatically build reference toolchain
This means that a simple:
$ make crossgcc
creates the reference toolchain in the correct directory. Thanks to the
dependency on the clean-for-update target, an existing .xcompile along
with any compiled objects in build/ will be cleaned out, so the next
build will automatically use the newly created reference toolchain.
Signed-off-by: Cristian Magherusan-Stanciu <cristi.magherusan@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6598
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Mon, 16 May 2011 00:05:50 +0000 (00:05 +0000)]
cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6597
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Marc Jones [Sun, 15 May 2011 23:13:54 +0000 (23:13 +0000)]
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6596
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Sun, 15 May 2011 22:40:40 +0000 (22:40 +0000)]
agesa_wrapper: Avoid repetitive Kconfig depends, trivial
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6595
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Scott Duplichan [Sun, 15 May 2011 22:10:15 +0000 (22:10 +0000)]
Cosmetic cleanup.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:09:09 +0000 (22:09 +0000)]
1) Remove unused kconfig options.
2) Correct UMA graphics PCI device ID.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593
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Scott Duplichan [Sun, 15 May 2011 22:07:56 +0000 (22:07 +0000)]
Update gpp port configuration.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:06:09 +0000 (22:06 +0000)]
Enable rom cache early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6591
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:05:00 +0000 (22:05 +0000)]
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6590
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:03:45 +0000 (22:03 +0000)]
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6589
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:02:27 +0000 (22:02 +0000)]
Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6588
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Scott Duplichan [Sun, 15 May 2011 22:00:23 +0000 (22:00 +0000)]
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6587
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:59:19 +0000 (21:59 +0000)]
Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6586
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Scott Duplichan [Sun, 15 May 2011 21:56:03 +0000 (21:56 +0000)]
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6585
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Scott Duplichan [Sun, 15 May 2011 21:54:04 +0000 (21:54 +0000)]
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:51:31 +0000 (21:51 +0000)]
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6583
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Scott Duplichan [Sun, 15 May 2011 21:48:22 +0000 (21:48 +0000)]
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582
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Scott Duplichan [Sun, 15 May 2011 21:45:46 +0000 (21:45 +0000)]
Build device paths for AP cores so that coreboot will report them to the OS.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6581
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Scott Duplichan [Sun, 15 May 2011 21:41:00 +0000 (21:41 +0000)]
Program the I/O APIC ID.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6580
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:38:08 +0000 (21:38 +0000)]
Enable AHCI mode and hide IDE controller to reduce boot time.
Note: enable AHCI in seabios and apply seabios patch:
http://www.mail-archive.com/seabios@seabios.org/msg00437.html
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6579
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:26:04 +0000 (21:26 +0000)]
Move mmconf base from
e0000000 to
f8000000 to avoid conflict with UMA BAR.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:19:54 +0000 (21:19 +0000)]
Fix ACPI shutdown function by removing reliance on SMI.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6577
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:18:59 +0000 (21:18 +0000)]
Configure CIMx to use 33 MHz fast mode for SPD read.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6576
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:13:00 +0000 (21:13 +0000)]
Match DIMM SPD addressing to implemented slots.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6575
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:11:41 +0000 (21:11 +0000)]
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6574
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:10:20 +0000 (21:10 +0000)]
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from
dfffffff to
fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6573
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:07:43 +0000 (21:07 +0000)]
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6572
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:06:30 +0000 (21:06 +0000)]
Correct the number of MCA error reporting banks cleared.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6571
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:01:42 +0000 (21:01 +0000)]
1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.
2) Remove coreboot variable MTRR initialization because AMD reference code handles it.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6570
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Fri, 13 May 2011 06:25:16 +0000 (06:25 +0000)]
siemens/sitemp_g1p1: Adapt read_option() to latest changes
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6569
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 12 May 2011 06:53:52 +0000 (06:53 +0000)]
Remove uart_init() in Siemens sitemp-g1p1
uart_init() was moved to common code in r6531, but I
missed that when integrating the new mainboard code.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6568
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Josef Kellermann [Wed, 11 May 2011 07:47:43 +0000 (07:47 +0000)]
Add Siemens SITEMP-G1 board
The code is loosely based on AMD dbm690t (and copied from there)
and adapted to match the Siemens SITEMP-G1 board.
It boots both Linux and Windows XP (and if it doesn't then complain
with me [Patrick] because in that case I must have messed it up when
integrating the patch)
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6567
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Patrick Georgi [Wed, 11 May 2011 07:44:27 +0000 (07:44 +0000)]
Work around unclean CMOS handling for now
Stefan switched away from #ifdef across the tree (and is absolutely right with that), but
unfortunately there are some special cases that trigger in even more special situations.
Revert one such change selectively. It's destined to go once CMOS is reworked.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6566
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Patrick Georgi [Tue, 10 May 2011 21:53:13 +0000 (21:53 +0000)]
Change read_option() to a macro that wraps some API uglyness
Simplify
read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
to
read_option(foo, somedefault)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565
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Vikram Narayanan [Tue, 10 May 2011 21:47:57 +0000 (21:47 +0000)]
This replaces the fixed shift values in the apic timer init with macros.
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6564
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Patrick Georgi [Tue, 10 May 2011 21:42:52 +0000 (21:42 +0000)]
Fix compilation error due to non-unix style line endings in cmos.layout file while generating option_table.h.
Windows, Mac and *nix type line endings are now taken care of.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6563
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Ivaylo Valkov [Mon, 9 May 2011 20:53:38 +0000 (20:53 +0000)]
Adds RS740 HT and internal graphics PCI ids.
Signed-off-by: Ivaylo Valkov <ivaylo@e-valkov.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6562
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Kerry She [Sat, 7 May 2011 09:15:02 +0000 (09:15 +0000)]
ADVANSUS A785E-I Mainboard support, Family10h ASB2, RS880(RS785E) + SB820 platform.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6561
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Kerry She [Sat, 7 May 2011 08:51:32 +0000 (08:51 +0000)]
RS780 DDI Lanes configure support,
and remove RS780 get_cpu_rev().
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6560
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Kerry She [Sat, 7 May 2011 08:43:40 +0000 (08:43 +0000)]
SB800 CIMX code can share the AGESA V5 lib code,
some platform only use sb800 cimx code, not use AGESA v5 code.
for such platform, one can compile the sb800 cimx and AGESA v5 lib code.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6559
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Kerry She [Sat, 7 May 2011 08:37:38 +0000 (08:37 +0000)]
1. move _mm_clflush_fs() to __SSE3__ block, because __builtin_ia32_sfence() is the sse built-in function
2. move the Amd Lib functions using sse build-in functions to __SSE3__ block
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6558
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 7 May 2011 08:33:14 +0000 (08:33 +0000)]
put the amdlib and agesa constant to .rodata segment.
so amdlib.c would not complain "Do not use global variables in romstage"
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6557
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Thu, 5 May 2011 16:49:11 +0000 (16:49 +0000)]
Adds VOID to empty parameter lists to get rid of some build warnings.
This change modifies a collection of files by adding the VOID parameter
to empty parameter lists to cut down on the number of warnings produced
when compiling the AMD Agesa code. This should cut down the number of
warnings by about 1100 each for rom- and ramstage.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6556
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Frank Vibrans [Thu, 5 May 2011 16:45:36 +0000 (16:45 +0000)]
Remove AMD Agesa requirement for standard include files
This change modifies Makefile.inc to add the -nostdinc flag to the default
CFLAGS value and removes the test for non-AMD Agesa builds. Other code is
added to the gcc-intrin.h file in the Agesa Include folder to make the
requirement for the standard includes obsolete from the Agesa perspective.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6555
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Sven Schnelle [Tue, 3 May 2011 07:55:43 +0000 (07:55 +0000)]
Enable caching for ROM area in model_6ex/cache_as_ram.inc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6554
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Sven Schnelle [Tue, 3 May 2011 07:55:30 +0000 (07:55 +0000)]
i82801gx: enable SPI prefetching
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6553
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Sven Schnelle [Mon, 2 May 2011 19:53:04 +0000 (19:53 +0000)]
Add option 'compress ramstage'
Add an option to make compression of ramstage configurable. Right now
it is always compressed. On my Thinkpad, the complete boot to grub takes
4s, with around 1s required for decompressing ramstage. This is probably
caused by the fact the decompression does a lot of single byte/word/qword
accesses, which are really slow on SPI buses. So give the user the option
to store ramstage uncompressed, if he has enough memory.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6552
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Scott Duplichan [Sat, 30 Apr 2011 00:22:04 +0000 (00:22 +0000)]
Sorry, my mistake.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6551
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Scott Duplichan [Sat, 30 Apr 2011 00:17:23 +0000 (00:17 +0000)]
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6550
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Sven Schnelle [Thu, 28 Apr 2011 09:29:06 +0000 (09:29 +0000)]
Thinkpad: Enable Battery events
Enable the following events for battery objects on
Thinkpad X60/T60:
24: BAT0 critical
25: BAT1 critical
4A: BAT0 present
4B: BAT0 state change
4C: BAT1 present
4D: BAT1 state change
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6549
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Sven Schnelle [Wed, 27 Apr 2011 19:48:05 +0000 (19:48 +0000)]
X60: enable Ultrabay if device is plugged in
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6548
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Wed, 27 Apr 2011 19:47:49 +0000 (19:47 +0000)]
T60: enable Ultrabay if device is plugged in
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6547
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Wed, 27 Apr 2011 19:47:42 +0000 (19:47 +0000)]
Lenovo PMH7: add pmh7_ultrabay_power_enable()
Can be used to enable/disable Ultrabay power on Thinkpads
who control that with the PMH7. (i.e. T60)
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6546
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Wed, 27 Apr 2011 19:47:28 +0000 (19:47 +0000)]
Lenovo H8: add h8_ultrabay_device_present()
returns 1 if a CDROM/HDD device is plugging in the
ultrabay. Return 0 if there's a battery or superio
extensions plugged in.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6545
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Tue, 26 Apr 2011 23:47:04 +0000 (23:47 +0000)]
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
example.
This newer version reflects the recent changes to further simplify the console
code and partly gets rid of some hacks in the previous version.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Fri, 22 Apr 2011 23:12:40 +0000 (23:12 +0000)]
Add (partly) support for Nuvoton NCT6776F
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6543
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Fri, 22 Apr 2011 23:10:35 +0000 (23:10 +0000)]
cosmetic changes to superiotool's nuvoton code
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6542
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Rudolf Marek [Fri, 22 Apr 2011 22:26:04 +0000 (22:26 +0000)]
Fix of fix copy and paste errors in ne2k.c (r6512 by stepan)
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6541
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Fri, 22 Apr 2011 02:32:03 +0000 (02:32 +0000)]
fix typo ttys0_index -> b_index
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6540
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Fri, 22 Apr 2011 02:17:26 +0000 (02:17 +0000)]
Get rid of all but one (I/O mapped) UART init functions.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6539
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Fri, 22 Apr 2011 01:45:11 +0000 (01:45 +0000)]
The UART divider should be calculated based on the base frequency
and baudrate, not hardcoded in addition to that.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6538
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Thu, 21 Apr 2011 21:26:58 +0000 (21:26 +0000)]
more ifdef -> if fixes.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6537
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Thu, 21 Apr 2011 20:45:45 +0000 (20:45 +0000)]
more ifdef -> if fixes
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Thu, 21 Apr 2011 20:24:43 +0000 (20:24 +0000)]
some ifdef --> if fixes
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Wed, 20 Apr 2011 22:23:56 +0000 (22:23 +0000)]
drop dead code from sb800 bootblock
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6534
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Wed, 20 Apr 2011 21:14:05 +0000 (21:14 +0000)]
drop excessive newline in uart8250.c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6533
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Wed, 20 Apr 2011 21:11:22 +0000 (21:11 +0000)]
Simplify coreboot's console/console.h
- shift most (romcc) code out of console.h into arch/x86/lib/romcc_console.c
- rename arch/x86/lib/printk_init.c to .../romstage_console.c
- drop FUNCTIONS_FOR_PRINT since __console_tx_* are already functions, so there
should not be any side effects to eliminating another indirection.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6532
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Wed, 20 Apr 2011 20:54:07 +0000 (20:54 +0000)]
run uart_init() from console_init, just like the other console initialization functions.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Wed, 20 Apr 2011 09:12:17 +0000 (09:12 +0000)]
Add Lenovo ThinkPad T60
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6530
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Wed, 20 Apr 2011 09:05:37 +0000 (09:05 +0000)]
PC87384: remove unused init function
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6529
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Wed, 20 Apr 2011 08:58:38 +0000 (08:58 +0000)]
pci1x2x: remove latency/bridge control/cacheline size settings
Those settings should be handled by the generic PCI/Cardbus code,
and not by the driver itself.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Wed, 20 Apr 2011 08:58:30 +0000 (08:58 +0000)]
pci1x2x: use cardbus_read_resources()/cardbus_enable_resources()
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6527
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Wed, 20 Apr 2011 08:58:16 +0000 (08:58 +0000)]
pci1x2x: use pci_ops set_subsystem instead of custom code
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6526
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Wed, 20 Apr 2011 08:58:08 +0000 (08:58 +0000)]
pci1x2x: add PCI1510 device IDs
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6525
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Wed, 20 Apr 2011 08:57:53 +0000 (08:57 +0000)]
pci1x2x: use devicetree register configuration
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6524
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Wed, 20 Apr 2011 01:08:25 +0000 (01:08 +0000)]
drop dead uart init code.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6523
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Wed, 20 Apr 2011 01:03:58 +0000 (01:03 +0000)]
fix boards that still had some uart init remainders
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6522
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Tue, 19 Apr 2011 21:33:40 +0000 (21:33 +0000)]
Drop baud rate init to an arbitrary baud rate from Super I/O code.
See discussion at
http://www.mail-archive.com/coreboot@coreboot.org/msg29394.html
config->com1, devicetree.cb cleanup and init_uart8250() removal
will follow once this patch is comitted
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Updated to drop com1, com2.... from config structure and devicetree.cb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6521
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Tue, 19 Apr 2011 19:57:26 +0000 (19:57 +0000)]
Lenovo PMH7: add pmh7_touchpad_enable()
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6520
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Tue, 19 Apr 2011 19:34:25 +0000 (19:34 +0000)]
Cast arguments to ctype(3) functions through (int)(unsigned char).
Signed-Off-By: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-By: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6519
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Idwer Vollering [Tue, 19 Apr 2011 19:21:27 +0000 (19:21 +0000)]
Fix compilation of all i82371eb boards when ACPI tables aren't generated
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6518
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Tue, 19 Apr 2011 06:40:56 +0000 (06:40 +0000)]
The "temp" will be used later. So it has to be calculated correctly.
Comment by Peter,
The variable name "temp" unfortunately does not explain what the value
is. The commit message also does not have hints. Hopefully in the
future it's possible to also use a brief moment to improve the clarity
of the code, while it is already being fixed for some other
reason. Ie. fixing up variable names, writing particularly informative
commit messages, or of course both at the same time! :)
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6517
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Tue, 19 Apr 2011 01:36:24 +0000 (01:36 +0000)]
Recently the 3 projects using the new AMD reference code have been
failing the check for globals (or statics) in romstage. This causes
ASRock E350M1, AMD Inagua, and AMD Persimmon builds to fail with the
message "Do not use global variables in romstage". The message is
working as intended. It is detecting data declared as 'static' when
'static const' was intended. The code executes correctly because it
never tries to modify the data.
To make reference code updates easy, it is probably best to avoid
modifying the AMD provided code if possible. The following change
bypasses the "Do not use global variables in romstage" check for
the AMD reference code only.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6516
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Tue, 19 Apr 2011 01:18:54 +0000 (01:18 +0000)]
Fix some more misuses of ifdef/if defined
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6515
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Tue, 19 Apr 2011 00:36:39 +0000 (00:36 +0000)]
cleanup wrong use of defined() after exporting all variables in Kconfig
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6514
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 18 Apr 2011 23:51:12 +0000 (23:51 +0000)]
* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value
to unify calls to *_enable_usbdebug()
* rename *_enable_usbdebug() to enable_usbdebug()
* move enable_usbdebug() to generic romstage console init code
and drop it from the individual romstage.c files.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 18 Apr 2011 02:26:56 +0000 (02:26 +0000)]
fix copy and paste errors in ne2k.c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6512
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 18 Apr 2011 02:07:16 +0000 (02:07 +0000)]
Emit unwritten symbols in Kconfig so we don't have to do constructs like
#if defined(CONFIG_FOO) && CONFIG_FOO anymore. This was partially implemented
but didn't work for symbols that were unset because of a missing dependency.
Patch taken from SeaBIOS.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6511
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Sun, 17 Apr 2011 14:55:21 +0000 (14:55 +0000)]
Lenovo H8 EC: add missing systemstatus.asl include
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6510
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sven Schnelle [Sun, 17 Apr 2011 12:54:32 +0000 (12:54 +0000)]
PMH7: Add dock event control
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6509
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sat, 16 Apr 2011 00:13:17 +0000 (00:13 +0000)]
Allow libpayload to use an OXPCIe 952 card on systems without
onboard serial port
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6508
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sat, 16 Apr 2011 00:09:53 +0000 (00:09 +0000)]
bootblock updates:
- allow CPU to define bootblock code, too.
- drop unneeded __PRE_RAM__ define
- move CBFS specific code out of bootblock_common.h into cbfs.h
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6507
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Fri, 15 Apr 2011 09:01:42 +0000 (09:01 +0000)]
sorry for breaking the tree.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6506
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Fri, 15 Apr 2011 04:12:03 +0000 (04:12 +0000)]
comment cosmetics in bootblock.ld
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6505
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Fri, 15 Apr 2011 03:34:05 +0000 (03:34 +0000)]
add FILO easy payload option
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6504
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Fri, 15 Apr 2011 03:30:03 +0000 (03:30 +0000)]
Handle drivers/ equally to any other sub directory.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6503
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Fri, 15 Apr 2011 00:19:27 +0000 (00:19 +0000)]
fix mainboards that were including earlymtrr.c without actually using it.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6502
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Thu, 14 Apr 2011 22:28:00 +0000 (22:28 +0000)]
drop half an uart8250 implementation from smiutil and use the common code
for that instead. This also allows using non-uart8250 consoles for smi
debugging.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6501
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Thu, 14 Apr 2011 21:05:41 +0000 (21:05 +0000)]
fix coreboot compilation without serial console enabled.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6500
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Thu, 14 Apr 2011 20:39:49 +0000 (20:39 +0000)]
earlymtrr.c: wipe some dead code, use names instead of numbers and some
cosmetics.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6499
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1