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(parent: 5c72a87) | patch
pci1x2x: remove latency/bridge control/cacheline size settings
authorSven Schnelle <svens@stackframe.org>
Wed, 20 Apr 2011 08:58:38 +0000 (08:58 +0000)
committerSven Schnelle <svens@stackframe.org>
Wed, 20 Apr 2011 08:58:38 +0000 (08:58 +0000)
commit81725b2effe9269e5079c6043077ba516e72aa82
tree36d93d3eaa95598bef4c64e6595aa454993cfa5etree | snapshot
parent5c72a8752bb5ce1c3b1bfb77c08039c71c2113efcommit | diff
pci1x2x: remove latency/bridge control/cacheline size settings

Those settings should be handled by the generic PCI/Cardbus code,
and not by the driver itself.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/mainboard/nokia/ip530/devicetree.cb diff | blob | history
src/southbridge/ti/pci1x2x/chip.h diff | blob | history
src/southbridge/ti/pci1x2x/pci1x2x.c diff | blob | history
my coreboot WIP stuff (asus m5a99x-evo board)