Enable caching for ROM area in model_6ex/cache_as_ram.inc

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 0906bc0e5fe350e0af2c34f83fe45ddbe538265e..02de5ab50ff2f39371a1ada5c2734f8632343c6e 100644 (file)
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -201,7 +201,17 @@ clear_mtrrs:
        xorl    %edx, %edx
        wrmsr
        movl    $MTRRphysMask_MSR(0), %ecx
-       movl    $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
+       movl    $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+       movl    $0x0000000f, %edx       // 36bit address space
+       wrmsr
+
+       /* Enable caching and Speculative Reads for the last 4MB. */
+       movl    $MTRRphysBase_MSR(1), %ecx
+       movl    $(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+       xorl    %edx, %edx
+       wrmsr
+       movl    $MTRRphysMask_MSR(1), %ecx
+       movl    $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
        movl    $0x0000000f, %edx       // 36bit address space
        wrmsr