* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value

  to unify calls to *_enable_usbdebug()
* rename *_enable_usbdebug() to enable_usbdebug()
* move enable_usbdebug() to generic romstage console init code
  and drop it from the individual romstage.c files.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/console/console.c b/src/console/console.c
index 4f11fbecf873363c1b83088f9be4fc4b46cd25f3..3178562bb342fb8185fec001c5d22e2ebed28aac 100644 (file)
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -95,6 +95,10 @@ int console_tst_byte(void)
 
 void console_init(void)
 {
+#if CONFIG_USBDEBUG
+       enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+       early_usbdebug_init();
+#endif
 #if CONFIG_CONSOLE_NE2K
        ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif

diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index aba31fcb3ca41a762aca0c83e9314c5e839d8a80..7905401336e18b79d11c22974c0e6e5dd8b0a9aa 100644 (file)
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -110,12 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        sb800_lpc_init();
 
        uart_init();
-#if CONFIG_USBDEBUG
-       sb800_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index ab43f46bd02ece1e47679dd15bf7d6ab98895049..ba9716a318a948a361f74a837746315250fd1b2a 100644 (file)
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -94,11 +94,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb600_enable_usbdebug(0);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 41fa2071ae14f10a3044efcab048ee9923b98cb6..e46d4bcdb6a0f7b93bfc0f3f800e157cad4d43c8 100644 (file)
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -93,11 +93,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 7bc96c8f43c20e93214419a0e3308f3818f6b430..a30403145742dfbb57bc086487fa41761a1ccb39 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 08cf32775ef6a9104a571043ee1b16194c464f6e..6627d747e2502231a0cf038de0bf76b6c9cda39c 100644 (file)
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -91,11 +91,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         * and it doesn't require any special setup. */
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb600_enable_usbdebug(0);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        post_code(0x03);

diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index fc9d611bbaefef6c411aa51b2ee69d8444b2ef81..ce24f03f715ac05439254dfc7886e6272458ebd4 100644 (file)
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -105,13 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index ce79e0d204ddf450bcd71577d180322fba11ccea..25822d9e566df75adb51744db707ec6c2e985570 100644 (file)
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -160,11 +160,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index eaa9edaace5f5c32ebe0b85500418d27fd32ceed..66a2b9ff1cc002f038f5ed407a21ef4331e5f5c1 100644 (file)
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -123,10 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        setup_mb_resource_map();
        uart_init();
        report_bist_failure(bist);
-#if CONFIG_USBDEBUG
-       mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
        console_init();
 
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);

diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 56204fb2300b27bc004aff7f707785402b167db1..68caa0120b8541669ad494fcb53c938044ce0e72 100644 (file)
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8712f_kill_watchdog();
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 56204fb2300b27bc004aff7f707785402b167db1..68caa0120b8541669ad494fcb53c938044ce0e72 100644 (file)
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8712f_kill_watchdog();
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 83cd91e72e2af6b469b9cf7c6d2df1bdbeb73d82..db20b832d8f21a1cb4c760fbef48091202174bda 100644 (file)
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -288,10 +288,6 @@ void main(unsigned long bist)
        /* Set up the console */
        uart_init();
 
-#if CONFIG_USBDEBUG
-       i82801gx_enable_usbdebug(1);
-       early_usbdebug_init();
-#endif
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index da6eb7701e2d50f59c0a0d54e98713dd101083fe..18187950ae4e3e1a0f0e30e617141a6cdde2757b 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -147,10 +147,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-       sis966_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
         console_init();
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 

diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 749b1d9a786f626c008d0c94b2f3ffe38d56758d..855d7558722d9a2575841f8f50e8cf4718550458 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -150,10 +150,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-       mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
         console_init();
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 

diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index d80df62b4e55c220c763082b126ff9ca1a0c31e6..f0585dbbb0eafbff05c01ec726bc8dcb50e2fba7 100644 (file)
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -102,11 +102,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8718f_disable_reboot();
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
        printk(BIOS_DEBUG, "\n");
 

diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 77e73b8c75a9fa6dde3872aedf32ec0e2ca8ed1c..694440fbebc1eff5d3709d2577ceff4ec0314767 100644 (file)
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8718f_disable_reboot();
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);

diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index e248a27d003b21ff086b9d7fd232488a01269048..5cd1fe571c337eae63090d959d33b3d40634c7cb 100644 (file)
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -239,11 +239,6 @@ void main(unsigned long bist)
        /* Set up the console */
        uart_init();
 
-#if CONFIG_USBDEBUG
-       i82801gx_enable_usbdebug(1);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 18fde1c7b51d6e476ee3113ccceb9e7b24f280de..772ee8a4379c83201079e5d8254f11ae8be6d3fc 100644 (file)
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -107,13 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 6dfc1444bdc3fc3102a0de0b9a61761f426f6a54..748cce7812566efb323e13ef4af9b97f9771bd02 100644 (file)
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -200,11 +200,6 @@ void main(unsigned long bist)
        /* Set up the console */
        uart_init();
 
-#if CONFIG_USBDEBUG
-       i82801gx_enable_usbdebug(1);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 05b0e8b40a942901f617360179477205c33c8636..3fd397255906d128d890d8ccd2f2744f165be5ab 100644 (file)
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -112,13 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 2cf73e651cdcce3ee03da0dfbb23e110a020ad6c..2fdcb74f21bde65c3d4329f72d2ed8a2c59987c4 100644 (file)
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -337,11 +337,6 @@ void main(unsigned long bist)
        /* Set up the console */
        uart_init();
 
-#if CONFIG_USBDEBUG
-       i82801gx_enable_usbdebug(1);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index fc792e6ad81b0d87d7cc2e6560347e1f6909728a..16a077f8f26a485a8f10935aa05b1b3ab8a6e15b 100644 (file)
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -96,11 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb600_enable_usbdebug(0);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 85b2241df6a795175c355bd5e165eb114a7224af..99540c9214dbc345489f2caca21cc4aead670509 100644 (file)
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -242,11 +242,6 @@ void main(unsigned long bist)
                uart_init();
        }
 
-#if CONFIG_USBDEBUG
-       i82801gx_enable_usbdebug(1);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 7fae43d7209000480f217de0addf239be1c707da..a9eb2736aafb0be8c854f70ae4244106aacc5d36 100644 (file)
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -139,10 +139,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        setup_mb_resource_map();
        uart_init();
        report_bist_failure(bist); /* Halt upon BIST failure. */
-#if CONFIG_USBDEBUG
-       mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
        console_init();
 
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);

diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 16baac29a562be59e40fc32ed98325165be3803a..d6101a734f89d9ed6c804154c4b36bea75416eb8 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -138,16 +138,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-       mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        val = cpuid_eax(1);
        printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);

diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 3929bf4ea802e1dd4f3ae7b5b275dc15614d8121..62ebfb8087dfa774e93336990ef10f01a9d89b08 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -140,10 +140,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-       mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
        console_init();
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 

diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 07976998c87c30c29dd856267dcb69b7bb59166a..ec8c4996d488ff64b727a3f5ca0de1148f8f4731 100644 (file)
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -272,11 +272,6 @@ void main(unsigned long bist)
        /* Set up the console */
        uart_init();
 
-#if CONFIG_USBDEBUG
-       i82801gx_enable_usbdebug(1);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index da0ab06a1a110cc6ebbc22a5b65a08d14c35a6d7..f34f8342ad0bd4d36b31fe07cde92771e7537db0 100644 (file)
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -125,12 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        sb7xx_51xx_disable_wideio(0);
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 1106f7caf9efe7de832940a7d0ff6f8bd39bec67..4af8f6ad5d10fb39b1448a4f630cf9d490d4c1c2 100644 (file)
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -100,11 +100,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8712f_kill_watchdog();
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb600_enable_usbdebug(0);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 1cead6ca633c45c310da43b9009cc1995d1fbdfd..0953d4c326442850def8911672be8dfa298da059 100644 (file)
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -95,11 +95,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8712f_kill_watchdog();
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb600_enable_usbdebug(0);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */

diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index f6116f978bfb6844478380ef5009a146a880bba7..eae4428c49c75706e25b09f37d6dab6de2f736b9 100644 (file)
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -136,10 +136,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-       mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
        console_init();
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 

diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index ed3ee8b4b4185cd68f11cdc79a228509467144cd..3699d097770bd6d24e3807fb3bfd2ea6dc0ba2fc 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -138,16 +138,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-       mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        val = cpuid_eax(1);
        printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);

diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig
index c32318c102442abbcede03bb6bc7e5013bd266a4..9b164b3758a80ad4fd6f29e7912ab39c9e9b4126 100644 (file)
--- a/src/southbridge/amd/sb600/Kconfig
+++ b/src/southbridge/amd/sb600/Kconfig
@@ -36,6 +36,10 @@ config EHCI_DEBUG_OFFSET
        hex
        default 0xe0
 
+config USBDEBUG_DEFAULT_PORT
+       int
+       default 0
+
 choice
        prompt "SATA Mode"
        default SATA_MODE_IDE

diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index b4d97b0da2ae85283c5d5c1c049670543a5b5675..3671686cb2d535e0a98777ec20332ab029d766bc 100644 (file)
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -30,7 +30,7 @@ void set_debug_port(unsigned int port)
        /* TODO: Allow changing the physical USB port used as Debug Port. */
 }
 
-void sb600_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
        device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
 

diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h
index 0ba107acc7b9b48637c535d43c2ed08346e5198a..97a7ad2638ba0bc45a93ed3bc25f7e7eb1bd4082 100644 (file)
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -40,5 +40,5 @@ void sb600_enable(device_t dev);
 void sb600_lpc_port80(void);
 void sb600_pci_port80(void);
 
-void sb600_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif /* SB600_H */

diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index b8d584a73cccf83e1c25c82504b56cf72d748a43..f263afefead375e616975f3b924c0ad1052aa272 100644 (file)
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -45,7 +45,7 @@ void set_debug_port(unsigned int port)
  * This code currently only supports the first one, i.e., USB Debug devices
  * attached to physical USB ports belonging to the first EHCI device.
  */
-void sb7xx_51xx_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
        device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
 

diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 741d244b86810931217842064420d62c582adde3..60eea47ee70f56bbb263d8c2f393fbcb2e5d118d 100644 (file)
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -75,5 +75,5 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 
-void sb7xx_51xx_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif /* SB700_H */

diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index d58437a68e5b15cb61ee981771d3d80903a710e3..174b0f2aa530c4e497604729bb23a823f5ddcacc 100644 (file)
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -43,7 +43,7 @@ void set_debug_port(unsigned int port)
 }
 
 
-void sb800_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
        pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5),
                           EHCI_BAR_INDEX, CONFIG_EHCI_BAR);

diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index caaeee992b1d4cd8fa1a016ccc23e88bbf268a1e..d7a4a38412229c35b7174cd8caa34a7c686893cb 100644 (file)
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -58,7 +58,7 @@ void sb800_clk_output_48Mhz(void);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 
-void sb800_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #else
 void sb800_enable(device_t dev);
 void __attribute__((weak)) sb800_setup_sata_phys(struct device *dev);

diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index afee190b2d08e36eec986f8930d346cde8532354..f63c12faaf8dc258e1e355267b05b45cbb0fa496 100644 (file)
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -24,11 +24,19 @@ config SOUTHBRIDGE_INTEL_I82801GX
        select HAVE_USBDEBUG
        select USE_WATCHDOG_ON_BOOT
 
+if SOUTHBRIDGE_INTEL_I82801GX
+
 config EHCI_BAR
        hex
-       default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX
+       default 0xfef00000
 
 config EHCI_DEBUG_OFFSET
        hex
-       default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX
+       default 0xa0
+
+config USBDEBUG_DEFAULT_PORT
+       int
+       default 1 
+
+endif
 

diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 63c583dea5b857901cbc6d03287ab4e6555e08f0..9b0bb1ffd3618dddb63613f16baad5e3a7332b30 100644 (file)
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -46,7 +46,7 @@ extern void i82801gx_enable(device_t dev);
 void enable_smbus(void);
 int smbus_read_byte(unsigned device, unsigned address);
 #endif
-void i82801gx_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif
 
 #define MAINBOARD_POWER_OFF    0

diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c
index 991aa5adaaededf2838dffe207ffd1e7732c3d06..ac7d3c2ed92f41b997193b95c67481d666356190 100644 (file)
--- a/src/southbridge/intel/i82801gx/usb_debug.c
+++ b/src/southbridge/intel/i82801gx/usb_debug.c
@@ -31,7 +31,7 @@ void set_debug_port(unsigned int port)
        /* Not needed, the ICH* southbridges hardcode physical USB port 1. */
 }
 
-void i82801gx_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
        u32 dbgctl;
        device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */

diff --git a/src/southbridge/intel/sch/usb_debug.c b/src/southbridge/intel/sch/usb_debug.c
index 58e0c330d860688d50b6223aa961d4cc709c654a..c3cfdedfabd2bf2e9162c36304fffc008e137e17 100644 (file)
--- a/src/southbridge/intel/sch/usb_debug.c
+++ b/src/southbridge/intel/sch/usb_debug.c
@@ -30,7 +30,7 @@ void set_debug_port(unsigned int port)
        /* Not needed, the southbridges hardcode physical USB port 1. */
 }
 
-void sch_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
        u32 dbgctl;
        device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */

diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index b89ae6fa49b4be29e84a5661921aa9edddaa03af..e7bf021c8e0026c7d63d0da66fa13e18c23b8247 100644 (file)
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -24,7 +24,7 @@
 #include "chip.h"
 
 void ck804_enable(device_t dev);
-void ck804_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 
 extern struct pci_operations ck804_pci_ops;
 

diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 3cccded343433b3b72017337254499a33b423e6b..361c67283349a0df238d420cf229d1bc51c17f4e 100644 (file)
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -46,7 +46,7 @@ void set_debug_port(unsigned int port)
        pci_write_config32(dev, 0x74, dword);
 }
 
-void ck804_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
        device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
 

diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index 2e78fa1ff655a4588a7ad5208531425d37d58cfb..be122d1c2025d28f5deb8a062d5511f968bbadb6 100644 (file)
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -40,7 +40,7 @@ void set_debug_port(unsigned int port)
        pci_write_config32(dev, 0x74, dword);
 }
 
-void mcp55_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
        device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
 

diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index 490a5f78e47fc27a4b348704ea9a053afbde868d..3173c50f3980fd4736f849bfaad0ca6df8e3b745 100644 (file)
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -35,7 +35,7 @@ extern struct pci_operations mcp55_pci_ops;
 #else
 #if !defined(__ROMCC__)
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-void mcp55_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif
 #endif
 

diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index fb20c960f392e03c6565ee32ba39cceb21e3358d..1be07d641b42532bf460cbc4a9a9e104917d6b19 100644 (file)
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -42,7 +42,7 @@ void set_debug_port(unsigned int port)
        pci_write_config32(dev, 0x74, dword);
 }
 
-void sis966_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
        device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
 

diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h
index a451bf7e55629918fb1abfb40fce675aadbd8f75..d6624b3062a451f4b865a41389cd1c16826327f2 100644 (file)
--- a/src/southbridge/sis/sis966/sis966.h
+++ b/src/southbridge/sis/sis966/sis966.h
@@ -40,7 +40,7 @@ void sis966_enable(device_t dev);
 #endif
 
 #if defined(__PRE_RAM__) && !defined(__ROMCC__)
-void sis966_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif
 
 #endif /* SIS966_H */