Stefan Reinauer [Sat, 4 Jun 2011 16:30:27 +0000 (16:30 +0000)]
WARNINGS_ARE_ERRORS is y per default, don't set it twice.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6637
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:48:14 +0000 (15:48 +0000)]
Port persimmon r6594 to e350m1: Cosmetic cleanup
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6636
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:47:56 +0000 (15:47 +0000)]
Port persimmon r6593 to e350m1: Remove unused Kconfig options
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6635
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:47:30 +0000 (15:47 +0000)]
Port persimmon r6592 to e350m1: Update GPP port configuration
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6634
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:47:05 +0000 (15:47 +0000)]
Port persimmon r6591 to e350m1: ROM cache early
Enable rom cache early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:46:50 +0000 (15:46 +0000)]
Port persimmon r6590 to e350m1: Work around memory allocation problem
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6632
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:46:32 +0000 (15:46 +0000)]
Port persimmon r6589 to e350m1: Strip down AGESA options
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6631
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:46:13 +0000 (15:46 +0000)]
Port persimmon r6588 to e350m1: VGA framebuffer
Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6630
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:45:46 +0000 (15:45 +0000)]
Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6629
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:45:29 +0000 (15:45 +0000)]
Port persimmon r6586 to e350m1: FADT revision
Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6628
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:45:12 +0000 (15:45 +0000)]
Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:44:54 +0000 (15:44 +0000)]
Port persimmon r6583 to e350m1: pstate 0 early
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:44:31 +0000 (15:44 +0000)]
Port persimmon r6582 to e350m1: 33 MHz SPI read early
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6625
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:44:14 +0000 (15:44 +0000)]
Port persimmon r6578 and r6596 to e350m1: MMCONF base
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6624
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:43:56 +0000 (15:43 +0000)]
Port persimmon r6574 to e350m1: MMCONF size
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6623
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:43:38 +0000 (15:43 +0000)]
Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from
dfffffff to
fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6622
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:43:15 +0000 (15:43 +0000)]
Port persimmon r6572 to e350m1: I/O APIC ID
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6621
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:40:12 +0000 (15:40 +0000)]
vt8237r: Simplify bootblock init to work around nested if() romcc problem
During the hackathon in Prague we discovered that romcc has a problem
compiling the previous nested if() statements correctly. This patch
makes the code a little simpler, and indeed works around the romcc issue.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6620
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marc Jones [Fri, 3 Jun 2011 19:59:52 +0000 (19:59 +0000)]
This patch sets max freq defaults for ddr2 and ddr3for fam10.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Alexandru Gagniuc [Fri, 3 Jun 2011 19:46:25 +0000 (19:46 +0000)]
Correct wrong PCI ID for VIA K8M890 Chrome.
With the K8T800/M800 patch from r6367 the PCI IDs for the VIA chrome were
moved to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly.
(3220 instead of 3230). This patch defines the correct PCI ID for this device.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6618
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Fri, 3 Jun 2011 10:14:56 +0000 (10:14 +0000)]
advansus/a785e-i mainboard enable warning as error
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6617
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Wed, 1 Jun 2011 19:54:16 +0000 (19:54 +0000)]
Really fix iasl filename issues in our build system
There's a remaining issue that iasl cuts of "\..*$" from
output paths, even if that substring contains "/" (ie.
across directories)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6616
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Wed, 1 Jun 2011 19:29:48 +0000 (19:29 +0000)]
Report build result from abuild (did all requested boards build?)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6615
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Wed, 1 Jun 2011 02:00:30 +0000 (02:00 +0000)]
trivial remove blanks at the end of line
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6614
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Wed, 1 Jun 2011 01:56:49 +0000 (01:56 +0000)]
This patch fix a AMD sb800 wrapper compile warning:
src/southbridge/amd/cimx_wrapper/sb800/late
call clear_ioapic but not include the prototype declare header file.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 23 May 2011 22:48:13 +0000 (22:48 +0000)]
We don't have pausing versions of single-IO instructions.
Hence remove the wrong comment.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6612
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 23 May 2011 22:43:43 +0000 (22:43 +0000)]
AP_IN_SIPI_WAIT is already defined in the CPU Kconfig of those boards.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6611
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Mon, 23 May 2011 17:55:20 +0000 (17:55 +0000)]
Correct implementation of r6608.
(.align actually takes its argument in bytes)
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6610
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 23 May 2011 17:16:44 +0000 (17:16 +0000)]
exclude src/vendorcode from GPLv2 license checks.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6609
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Sun, 22 May 2011 15:39:25 +0000 (15:39 +0000)]
Ensure ck804 romstrap is 16-byte aligned.
This alignment seems to be necessary for the chip to recognize it.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6608
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Sat, 21 May 2011 22:18:59 +0000 (22:18 +0000)]
Add regression test for build directory handling to make lint target
A couple of scenarios that were fixed in the last few revisions are
tested to ensure that it's easy to determine breakage.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6607
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 20 May 2011 23:31:41 +0000 (23:31 +0000)]
Handle absolute source file paths
We used to fail there because we unconditionally prefixed the relative directory where it was referenced.
Tested in various scenarios:
- obj=build
- obj=../obj
- obj=$PWD/../obj
- obj=/some/other/absolute/path
- obj=/./some/other/absolute/path
In-tree relative paths still work as before, the only change in behaviour is when a source file name (as specified in one of the *-y variables) starts with "/".
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6606
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 20 May 2011 23:08:12 +0000 (23:08 +0000)]
Handle both cases, obj being absolute and relative
gnu make's handling of filenames is less than optimal. It simply
compares strings, so foo/../bar is different from bar, even though
they're logically the same.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6605
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 20 May 2011 22:17:58 +0000 (22:17 +0000)]
Fix building with relative path to object directory outside the source tree
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6604
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 20 May 2011 22:16:49 +0000 (22:16 +0000)]
iasl still can't cope with extra "." in file paths
It's really a work around, but given how this issue seems to come
back again and again, let's work around it.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6603
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 20 May 2011 22:14:07 +0000 (22:14 +0000)]
Fix ccache behaviour if more than one ccache in PATH
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6602
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Fri, 20 May 2011 17:50:14 +0000 (17:50 +0000)]
Correct amd persimmon romstage code for early SPI prefetch enable.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Fri, 20 May 2011 00:06:09 +0000 (00:06 +0000)]
Move the ACPI FACP table to the front of the RSDT list. This is done to work around a Windows XP or Server 2003 setup failure where an error message such as: "An unexpected error (
805262864) occurred at line 1768 of d:\xpclient\base\boot\setup\arcdisp.c" occurs. This change updates AMD reference board projects, but could applied to others as well.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6600
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Mon, 16 May 2011 15:32:28 +0000 (15:32 +0000)]
Move crossgcc rules to coreboot specific Makefile
Toplevel Makefile should (as far as possible) be coreboot-agnostic,
we have Makefile.inc for that.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6599
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Cristian Magherusan-Stanciu [Mon, 16 May 2011 01:35:03 +0000 (01:35 +0000)]
Add crossgcc target to automatically build reference toolchain
This means that a simple:
$ make crossgcc
creates the reference toolchain in the correct directory. Thanks to the
dependency on the clean-for-update target, an existing .xcompile along
with any compiled objects in build/ will be cleaned out, so the next
build will automatically use the newly created reference toolchain.
Signed-off-by: Cristian Magherusan-Stanciu <cristi.magherusan@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6598
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Mon, 16 May 2011 00:05:50 +0000 (00:05 +0000)]
cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6597
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marc Jones [Sun, 15 May 2011 23:13:54 +0000 (23:13 +0000)]
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6596
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sun, 15 May 2011 22:40:40 +0000 (22:40 +0000)]
agesa_wrapper: Avoid repetitive Kconfig depends, trivial
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6595
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:10:15 +0000 (22:10 +0000)]
Cosmetic cleanup.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:09:09 +0000 (22:09 +0000)]
1) Remove unused kconfig options.
2) Correct UMA graphics PCI device ID.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:07:56 +0000 (22:07 +0000)]
Update gpp port configuration.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:06:09 +0000 (22:06 +0000)]
Enable rom cache early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6591
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:05:00 +0000 (22:05 +0000)]
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6590
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:03:45 +0000 (22:03 +0000)]
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6589
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:02:27 +0000 (22:02 +0000)]
Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6588
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 22:00:23 +0000 (22:00 +0000)]
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6587
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:59:19 +0000 (21:59 +0000)]
Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6586
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:56:03 +0000 (21:56 +0000)]
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6585
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:54:04 +0000 (21:54 +0000)]
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:51:31 +0000 (21:51 +0000)]
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6583
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:48:22 +0000 (21:48 +0000)]
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:45:46 +0000 (21:45 +0000)]
Build device paths for AP cores so that coreboot will report them to the OS.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6581
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:41:00 +0000 (21:41 +0000)]
Program the I/O APIC ID.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6580
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:38:08 +0000 (21:38 +0000)]
Enable AHCI mode and hide IDE controller to reduce boot time.
Note: enable AHCI in seabios and apply seabios patch:
http://www.mail-archive.com/seabios@seabios.org/msg00437.html
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6579
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:26:04 +0000 (21:26 +0000)]
Move mmconf base from
e0000000 to
f8000000 to avoid conflict with UMA BAR.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:19:54 +0000 (21:19 +0000)]
Fix ACPI shutdown function by removing reliance on SMI.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6577
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:18:59 +0000 (21:18 +0000)]
Configure CIMx to use 33 MHz fast mode for SPD read.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6576
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:13:00 +0000 (21:13 +0000)]
Match DIMM SPD addressing to implemented slots.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6575
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:11:41 +0000 (21:11 +0000)]
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6574
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:10:20 +0000 (21:10 +0000)]
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from
dfffffff to
fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6573
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:07:43 +0000 (21:07 +0000)]
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6572
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:06:30 +0000 (21:06 +0000)]
Correct the number of MCA error reporting banks cleared.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6571
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sun, 15 May 2011 21:01:42 +0000 (21:01 +0000)]
1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.
2) Remove coreboot variable MTRR initialization because AMD reference code handles it.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6570
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Fri, 13 May 2011 06:25:16 +0000 (06:25 +0000)]
siemens/sitemp_g1p1: Adapt read_option() to latest changes
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6569
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 12 May 2011 06:53:52 +0000 (06:53 +0000)]
Remove uart_init() in Siemens sitemp-g1p1
uart_init() was moved to common code in r6531, but I
missed that when integrating the new mainboard code.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6568
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Wed, 11 May 2011 07:47:43 +0000 (07:47 +0000)]
Add Siemens SITEMP-G1 board
The code is loosely based on AMD dbm690t (and copied from there)
and adapted to match the Siemens SITEMP-G1 board.
It boots both Linux and Windows XP (and if it doesn't then complain
with me [Patrick] because in that case I must have messed it up when
integrating the patch)
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6567
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Wed, 11 May 2011 07:44:27 +0000 (07:44 +0000)]
Work around unclean CMOS handling for now
Stefan switched away from #ifdef across the tree (and is absolutely right with that), but
unfortunately there are some special cases that trigger in even more special situations.
Revert one such change selectively. It's destined to go once CMOS is reworked.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6566
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 10 May 2011 21:53:13 +0000 (21:53 +0000)]
Change read_option() to a macro that wraps some API uglyness
Simplify
read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
to
read_option(foo, somedefault)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565
2b7e53f0-3cfb-0310-b3e9-
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Vikram Narayanan [Tue, 10 May 2011 21:47:57 +0000 (21:47 +0000)]
This replaces the fixed shift values in the apic timer init with macros.
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6564
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 10 May 2011 21:42:52 +0000 (21:42 +0000)]
Fix compilation error due to non-unix style line endings in cmos.layout file while generating option_table.h.
Windows, Mac and *nix type line endings are now taken care of.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6563
2b7e53f0-3cfb-0310-b3e9-
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Ivaylo Valkov [Mon, 9 May 2011 20:53:38 +0000 (20:53 +0000)]
Adds RS740 HT and internal graphics PCI ids.
Signed-off-by: Ivaylo Valkov <ivaylo@e-valkov.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6562
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 7 May 2011 09:15:02 +0000 (09:15 +0000)]
ADVANSUS A785E-I Mainboard support, Family10h ASB2, RS880(RS785E) + SB820 platform.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6561
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 7 May 2011 08:51:32 +0000 (08:51 +0000)]
RS780 DDI Lanes configure support,
and remove RS780 get_cpu_rev().
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6560
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 7 May 2011 08:43:40 +0000 (08:43 +0000)]
SB800 CIMX code can share the AGESA V5 lib code,
some platform only use sb800 cimx code, not use AGESA v5 code.
for such platform, one can compile the sb800 cimx and AGESA v5 lib code.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6559
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 7 May 2011 08:37:38 +0000 (08:37 +0000)]
1. move _mm_clflush_fs() to __SSE3__ block, because __builtin_ia32_sfence() is the sse built-in function
2. move the Amd Lib functions using sse build-in functions to __SSE3__ block
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6558
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 7 May 2011 08:33:14 +0000 (08:33 +0000)]
put the amdlib and agesa constant to .rodata segment.
so amdlib.c would not complain "Do not use global variables in romstage"
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6557
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Thu, 5 May 2011 16:49:11 +0000 (16:49 +0000)]
Adds VOID to empty parameter lists to get rid of some build warnings.
This change modifies a collection of files by adding the VOID parameter
to empty parameter lists to cut down on the number of warnings produced
when compiling the AMD Agesa code. This should cut down the number of
warnings by about 1100 each for rom- and ramstage.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6556
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Thu, 5 May 2011 16:45:36 +0000 (16:45 +0000)]
Remove AMD Agesa requirement for standard include files
This change modifies Makefile.inc to add the -nostdinc flag to the default
CFLAGS value and removes the test for non-AMD Agesa builds. Other code is
added to the gcc-intrin.h file in the Agesa Include folder to make the
requirement for the standard includes obsolete from the Agesa perspective.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6555
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Tue, 3 May 2011 07:55:43 +0000 (07:55 +0000)]
Enable caching for ROM area in model_6ex/cache_as_ram.inc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6554
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Tue, 3 May 2011 07:55:30 +0000 (07:55 +0000)]
i82801gx: enable SPI prefetching
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6553
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Mon, 2 May 2011 19:53:04 +0000 (19:53 +0000)]
Add option 'compress ramstage'
Add an option to make compression of ramstage configurable. Right now
it is always compressed. On my Thinkpad, the complete boot to grub takes
4s, with around 1s required for decompressing ramstage. This is probably
caused by the fact the decompression does a lot of single byte/word/qword
accesses, which are really slow on SPI buses. So give the user the option
to store ramstage uncompressed, if he has enough memory.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6552
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sat, 30 Apr 2011 00:22:04 +0000 (00:22 +0000)]
Sorry, my mistake.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6551
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Sat, 30 Apr 2011 00:17:23 +0000 (00:17 +0000)]
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6550
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Thu, 28 Apr 2011 09:29:06 +0000 (09:29 +0000)]
Thinkpad: Enable Battery events
Enable the following events for battery objects on
Thinkpad X60/T60:
24: BAT0 critical
25: BAT1 critical
4A: BAT0 present
4B: BAT0 state change
4C: BAT1 present
4D: BAT1 state change
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6549
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Wed, 27 Apr 2011 19:48:05 +0000 (19:48 +0000)]
X60: enable Ultrabay if device is plugged in
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6548
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Wed, 27 Apr 2011 19:47:49 +0000 (19:47 +0000)]
T60: enable Ultrabay if device is plugged in
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6547
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Wed, 27 Apr 2011 19:47:42 +0000 (19:47 +0000)]
Lenovo PMH7: add pmh7_ultrabay_power_enable()
Can be used to enable/disable Ultrabay power on Thinkpads
who control that with the PMH7. (i.e. T60)
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6546
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Wed, 27 Apr 2011 19:47:28 +0000 (19:47 +0000)]
Lenovo H8: add h8_ultrabay_device_present()
returns 1 if a CDROM/HDD device is plugging in the
ultrabay. Return 0 if there's a battery or superio
extensions plugged in.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6545
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Tue, 26 Apr 2011 23:47:04 +0000 (23:47 +0000)]
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
example.
This newer version reflects the recent changes to further simplify the console
code and partly gets rid of some hacks in the previous version.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Fri, 22 Apr 2011 23:12:40 +0000 (23:12 +0000)]
Add (partly) support for Nuvoton NCT6776F
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6543
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Fri, 22 Apr 2011 23:10:35 +0000 (23:10 +0000)]
cosmetic changes to superiotool's nuvoton code
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6542
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Fri, 22 Apr 2011 22:26:04 +0000 (22:26 +0000)]
Fix of fix copy and paste errors in ne2k.c (r6512 by stepan)
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6541
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Fri, 22 Apr 2011 02:32:03 +0000 (02:32 +0000)]
fix typo ttys0_index -> b_index
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6540
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Fri, 22 Apr 2011 02:17:26 +0000 (02:17 +0000)]
Get rid of all but one (I/O mapped) UART init functions.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6539
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Fri, 22 Apr 2011 01:45:11 +0000 (01:45 +0000)]
The UART divider should be calculated based on the base frequency
and baudrate, not hardcoded in addition to that.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6538
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1