Make libpayload alloc() memory pointers volatile

gcc4.6.2 was optimizing the libpayload alloc() function and failing to
reload a pointer after the memory had been manipulated by a pointer in
the inlined function setup(). Change the pointer type to volatile
and now pass it to the setup() function. Also clean up the
declaration so that it isn't cast a bunch times in the function.

Change-Id: I1637bd7bd5d9cf82ac88925cbfe76d319aa3cd82
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/705
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

If the memory mapped UART isn't present, leave it out of the cb tables.

This way u-boot won't try to use a UART that isn't plugged in.

Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/729
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)

tell superiotool about the ITE 8772

no dumping yet

Change-Id: I4e687ca816c8d6d1c95255b0abf6a19513e23f86
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/734
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

Increase size of the coreboot table area

Packing a device tree into the coreboot table can easily make
the table exceed the current limit of 8KB. However, right now
there is no error handling in place to catch that case.

Increase the maximum memory usable for all tables from 64KB to
128KB and increase the maximum coreboot table size from 8KB
to 32KB.

Change-Id: I2025bf070d0adb276c1cd610aa8402b50bdf2525
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/704
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Fix compilation when USE_OPTION_TABLE is not defined.

Change-Id: Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/702
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Fix coreboot table size calculations.

The code when reporting the coreboot table size did not account
for the last added table record. This change fixes the problem.

 . rebuild coreboot, program it on the target, restart it
 . look for 'Wrote coreboot table at:' in the console log
 . observe the adequate table size reported

 $  grep 'Wrote coreboot table:' /tmp/cb.log
 Wrote coreboot table at: 00000500, 0x10 bytes, checksum c06f
 Wrote coreboot table at: 7f6fc000, 0x1a73 bytes, checksum 3e45
 $

Change-Id: Ic55501a4ae06fab2bcda9aea58e362325f2edccf
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/703
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Clean up use of CONFIG_ variables in coreboot_table.c

CONFIG_ variables are used inconsistently within the file
src/arch/x86/boot/coreboot_table.c. #ifdef will do the wrong
thing if the option is disabled. #if (CONFIG_FOO == 1) is
not needed.

Change-Id: Ifcac6ceac5fb34b931281beae500023597b3533b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/701
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

Fix dependency problem for uart8250.c as well

If you build in parallel, option_table.h will occasionally not be there yet
and the build will fail.

Change-Id: I828956ab2e05c48d20c2f7c55616cc8fa19e1227
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/698
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Fix compilation with CONFIG_USE_OPTION_TABLE enabled

Change-Id: I6c5d973442bc1770702180a8964f1bf6ed6062ed
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/696
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Add helper function to find a Local APIC by ID in the device tree.

Change-Id: Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/695
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Don't try to compute I/O for empty sub buses.

I am not sure if the sub bus being 0 is a problem, or if the assumption
there has to be at least one non empty link is just wrong. It certainly
does not hurt to add a small consistency check in either case.

Change-Id: I098446deef96a8baae26a7ca1ddd96e626a06dc5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/693
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

OXPCIe: Reinitialize UART after pci_dev_set_resources()

... and only pull in early init code if the OXPCIe is used for console.

Change-Id: I01feca3b9e8376a75c17554ba1bd200d523dff8d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/692
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

move console includes to central console/console.h

Because it's included everywhere anyways.

Change-Id: I99a9e6edac08df57c50ef3a706fdbd395cad0abc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/691
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Add support for the Startech PEX1XS1PMINI

It has a smaller footprint than the already supported MPEX2S952

Change-Id: Ie36b67f9628882d516ca34ff164f0e8918955a5b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/690
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Don't run any Option ROMs stored outside of the system flash

Right now coreboot only executes VGA Option ROMs. However, this is not
good enough. For security reasons we want to execute only Option ROMs
stored in our r/o CBFS.

This patch adds a new option to disable execution of arbitrary Option
ROMs.

Also fix the capitalization of Option ROM in src/devices/Kconfig

Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/730
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Mathias Krause <minipli@googlemail.com>

Add an implementation for the memchr library function

Change-Id: Icded479d246f7cce8a3d2154c69f75178fa513e1
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/708
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>

Fix lint-stable checkin hooks on MacOS X

- wc adds a number of leading spaces which broke cut
- sed can't replace spaces with new lines, so use tr for that.
- make sure directories are created if they're not there.

Change-Id: Ia0db059683abe3d97b0ab6feaece660a1f4e5079
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/774
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

Don't run VGA option ROMs on S3 resume.

This will save us a few 100 ms on resume.

Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/715
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Unify Local APIC address definitions

We used several names for that same value, and hardcoded the value
at some more places.

They're all LOCAL_APIC_ADDR now (except for lapic specific code
that still uses LAPIC_DEFAULT_BASE).

Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Add support for A-Open DXPL Plus-U motherboard

This is an old (pre-2005) entry-level server mainboard. The code
is adapted from mainboard/intel/xe7501devkit.

Featured chips:
 - Dual socket604
 - E7505 northbridge
 - 82801DB southbridge (with EHCI debug port)
 - 82870p2 PCI-X bridge
 - LPC47M102S-MC super-io
 - 512kB FWH flash (flashrom does the job well)

What works:
 - Dual-Xeon P4/HT boot with microcode update
 - RAM: registered ECC DDR266 in dual-channel
 - PCI-X slot interrupts with ACPI and I/O apic
 - On-board PCI-X GbE and SCSI
 - ACPI power-off and wakeup with PME#

Notes :
 - Current ACPI is more or less a mess
 - Interrupts do not route correctly with PIRQ
 - MP-table is not implemented
 - Issues with reboots remain (cold and warm)
 - Many superio devices are disabled by default
 - Audio codec is not investigated

Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/303
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Move C labels to start-of-line

Also mark the corresponding lint test stable.

Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

lint: test that labels begin at start-of-line

Some attempt at enforcing style

Change-Id: Ibbfb86402ecc57e8db6c3857c8e0193085ed4fc2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/771
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

correctly mark code segments as code in SELF

In bios_log, find that the first segment of the payload is shown
as code rather than data.

Sample:
       Got a payload
       Loading segment from rom address 0xfff29378
         code (compression=1)
       ...

Change-Id: I82eaad23f08c02f4ed75744affa8835255cf5c17
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/767
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

selfboot: drop dead code

As a left over from elfboot times, selfboot keeps the segments to
load in the order in which they appeared in the original file as
well as in the order they will later appear in memory. This is not
needed in selfboot, so drop the code and structure members that handle
the in-file order.

Change-Id: I6be7a3a1bdf717fec1ee8e5b3227c63150580b41
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/768
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Revert "Use -mno-sse to prevent overzealous gcc optimizations"

AGESA uses SSE intrinsics :-(

This reverts commit 05f4b03fb64999ba373fe61256f358e5371bf8ae

Change-Id: I7c48e07a261eafda2119354d282bd05eac5a14b6
Reviewed-on: http://review.coreboot.org/706
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

Use -mno-sse to prevent overzealous gcc optimizations

The offending part that made coreboot crash with some toolchains
was that gcc emits SSE instructions but coreboot did not enable SSE at
that point.

Since the gain for coreboot using SSE instructions is not measurable,
let's not use SSE instructions rather than enabling SSE early on.
One rationale behind this is that other parts of coreboot, like the
SMM handler would need fixing because the XMM registers are not saved
on SMM entry. Thus keep it simple.

Change-Id: I14f0942f300085767ece44cec570fb15c761e88d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/694
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Fix ECC disable option for AMD Fam10 DDR2 and DDR3.

The logic was backwards on the ECC enable/disable option. Also added better
debug output when the debug RAM init feature is enabled.

Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/670
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

gitconfig: Add lint-stable as pre-commit hook

When configuring the tree with "make gitconfig", a pre-commit hook
is installed that runs the stable lint tests.
If any of these fail, the log is visible (on stdout) and the
commit is aborted.

Change-Id: Ie2a26e87f466c63b24db8dca8827057a18ac7f3e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/682
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

lint: create two classes of tests, stable and dev

We have tests that pass (and should be enforced soonish) and those
that don't pass yet (and thus shouldn't break the build).

The plan is simple: As soon as a test passes, it's marked stable so
things remain that way.

"make lint" runs all tests,
"make lint-stable" runs only those that shouldn't fail.

Change-Id: Iaa85d71141606d9756e29b37c7a34c2a15e573ac
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/681
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix lint test for build directories

config files are rename()d, which fails across filesystem borders.
So force temporary config files in current directory.

Change-Id: I583c2ab9a822a6f99f838778aa17ffd2d47eaed1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/680
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Drop support for BROKEN marker

We used to support marking boards broken. We don't need that anymore.

Change-Id: I9d21fdf22c9a8e0e69488fc7896f2a81bf629201
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/675
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Rename vendor identifiers in Kconfig

Board identifiers use them without underscore, too. Unify that.

Change-Id: I146384ef6dbe601ad131dada8224f43e6c18433d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/674
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix x86 cpu_phys_address_size

After CPUID, requested feature flag is in edx, not eax.

Change-Id: I9ce27c22186f17cc64986be342d7d1ac78a79898
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/688
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>

tint requires more heap space for PDCurses.

tint was failing with the message "initscr(): Unable to create curscr."
tint uses the initscr() to enable vga windows, which allocates more
heap space with PDCurses than with tinycurses. Expanding the heap from
16KB to 64KB resolves the issue.

Change-Id: I1d38651e2b77f55613969c29614fb3b2be38a00c
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/687
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Marc Jones <marcj303@gmail.com>

AMD southbridge: remove sp5100

Southbridge SP5100 support was compiled with SB700 code, but static
device info structure would use sp5100/chip.h. To solve this drop
support for separate chip sp5100 and adjust the relevant Kconfig
options.

Removes chip directory:
  src/southbridge/amd/sp5100/

Rename Kconfig option
 from: SOUTHBRIDGE_AMD_SP5100
   to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100

Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/679
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>

asus/m4a785t-m: correct the CPU microcode patch selection

Thanks to ruik on #coreboot Freenode IRC channel for
  explaining to me how to get the cpu revision:
    Feb 21 22:07:32 <ruik>  ruik@ruik:~/coreboot$ cpuid | grep ^00000001
    Feb 21 22:07:32 <ruik>  00000001 00020f32 00020800 00000001 178bfbff
    [..]
    Feb 21 22:07:44 <ruik>  the 20f32 is mine CPUID
The rest was just looking at the correspondance in
  src/cpu/amd/model_10xxx/update_microcode.c
  like Marc Jones explained(thanks Marc Jones) in the mailing list here:
  http://www.coreboot.org/pipermail/coreboot/2012-February/068332.html

Change-Id: Ie0f004990e6b65456de009a4dcc306498bdb47e9
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/669
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)

Ati video: Apply un-written naming rules

Rename Kconfig to match directory name.

Change-Id: Idebc203bbc9a02599dfc3e65be021aa9e1b23d61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/678
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Revert "Fix multipleVGA cards resource conflict on Windows"

This reverts commit 8660a1aa56caeb31bfaf15464285ca650638515e

This commit has been found to cause problems with vbios and option rom init
in seabios. It has been found by several people and requires more analysis
before being recommitted.

Change-Id: Ie5f54e417e7a0d8bd8ca4c0a573976afeaa9e230
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/671
Tested-by: build bot (Jenkins)
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>

ACPI: More ../../.. removal

CPP is ran with src/ as part of its search path, so
using <northbridge/...> and the like is safe.

Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/649
Tested-by: build bot (Jenkins)

amd/sb600: Move HAVE_HARD_RESET to southbridge

No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/660
Tested-by: build bot (Jenkins)

Remove old AMD fam10 fixme comment

The family10 code had a very slow decompress before the cache settings were
fixed. This has been fixed for some time. Remove all the old messages from the
serial stream.

Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/672
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

libpayload: fix compile error with enabled USB_DEBUG

Commit c4348d0 ("libpayload: Remove bitfield use from OHCI data
structures") missed to adapt a debug message. This patch fixes this.

Change-Id: I5f6a4be9c7f6f99cb103926772717e15a3cbca70
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/653
Tested-by: build bot (Jenkins)
Reviewed-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>

Force SB600 bootblock to use I/O for PCI config

If PCI config cycles use MMIO instead of I/O in the SB600 bootblock
code the cycles will go nowhere since the MMIO feature hasn't been
configured yet. This change forces the cycles to use I/O and
configures the southbridge decode range to what is defined by the
mainboards Kconfig.

Change-Id: I85297237f32f37b3fc1ff5b488cca0a43bcf20fd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/632
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Force SB700 bootblock code to use I/O for PCI config cycles.

If PCI config cycles use MMIO instead of I/O in the SB700
bootblock code the cycles will go nowhere since the MMIO feature
hasn't been configured yet. This change forces the cycles to use
I/O and configures the southbridge decode range to what is specified
by the mainboards Kconfig.

Change-Id: I15a89a27645edf594d14ef20f129f75a315e9672
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/631
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Force SB800 bootblock to use I/O for PCI config

If PCI config cycles use MMIO instead of I/O in the bootblock
code the cycles will go nowhere since the MMIO feature hasn't been
configured yet. This change forces the cycles to use I/O.

Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/630
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.

The MTRR check for WB TOM2 setting was only checking revF, not extended family
revisions. All families above revf indicate 0xf in the family field and have
additional bits in the extended family field.

Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/627
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Torpedo mainboard changes to fix warnings.

Fixes the warnings generated in the torpedo mainboard build.  Most of these
changes are similar to fixes already implemented in the persimmon mainboard.

Change-Id: Ib931be51c0e6448c00c8cfeb13073e1f392582a5
Signed-off-by: Martin L Roth <martin@se-eng.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fixes Fam10/SR5650 cpu not recognized message.

Extend the Family10 revisions checked byt the printk message.

Change-Id: Ia94daeefb1aabfb128c577b1e0aa52cf63d5cf44
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/633
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

IEI-Kino Fam10 MPtable fix.

Make changes to MPtable to match the ACPI tables.

Change-Id: Icc18c9a25695d01d88d6ee5367064d527cc42bc1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/629
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

IEI Kino Fam10 ACPI table fixes.

Fix the ACPI IRQ routing. Also, fix the SSDT generations and TOM2 fixup.

Change-Id: Ica4a992d11bab63a510238dcd468b9fe80136def
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/628
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

nvidia/mcp55: Move HAVE_HARD_RESET to southbridge

No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/659
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

amd/sb700: Move HAVE_HARD_RESET to southbridge

No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/661
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

intel/i82801cx: Move HAVE_HARD_RESET to southbridge

No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: Ifba0b65d81af60774f368d151e935ae1cc768336
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/662
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

sis/sis966: Move HAVE_HARD_RESET to southbridge

No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: I9762ef01fc10c453ef643599c1c5dc8ee78081c3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/663
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

intel/i82801ex: Move HAVE_HARD_RESET to southbridge

No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/664
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

intel/sch: Move HAVE_HARD_RESET to southbridge

No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: I521deecf58e5d5de303f1ef2f5ff7e965294de18
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/665
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

amd/sb800: Move HAVE_HARD_RESET to southbridge

No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge. (cimx/sb800 is a "different"
chipset)

Change-Id: If7cf2a141a1f2df60f687c51fbd760aa405c8480
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/666
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

broadcom/bcm5785: Move HAVE_HARD_RESET to southbridge

No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: Id95660f088c8240606d45abf326cd5eefca30da3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/658
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

libpayload: enforce const correctness for CMOS getter/setter

Input only arguments to {get,set}_option*() should be const to catch
programming errors early.

Change-Id: I560001a8e9226dfd156a4e529fcad20549236ebd
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/652
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Avoid ../../.. paths in ASL files

The current directory is always part of the search path of cpp when
using #include "..."

Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/648
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Rename i945 ACPI files to not carry an i945_ prefix

In the spirit of the earlier renames.

Change-Id: I458a42c79a164483120169d1822ffa6861cc3aff
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/647
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: fix compiler warning for first_cmos_entry()

The 'name' argument to lookup_cmos_entry() is declared to be 'char *'
but we pass an empty string ("") which is 'const char[]' so the compiler
legitimatly warns about discarded qualifiers here. Fix this by passing
NULL as 'name'.

Minor nitpick: The NULL test in lookup_cmos_entry() is superfluous as our
implementation of strnlen() can handle NULL pointers gracefully. But for
an average C hacker it just doesn't feel right not to do so.

Change-Id: I592917d12d8fa840804c0d19e38b844427064fef
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/651
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

nvidia/ck804: Move HAVE_HARD_RESET to southbridge

No in-tree ck804-using board has it not selected, so move
selection from boards to southbridge.

Change-Id: I3064b406cfd5ad18067c597bd5b5866a720f7e87
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/657
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Remove whitespace.

Fix issues reported by new lint test.

Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

lint: Add test for whitespace issues in the code

So far it tests for trailing whitespace.
"Upstream" files (bison/flex's .?_shipped, kconfig, vendorcode) are ignored.

Change-Id: I7af1954d537fd05f06cd210ac130dac87892159b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/645
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

amd/amd8111: Move HAVE_HARD_RESET to southbridge

No in-tree amd8111-using board has it not selected, so move
selection from boards to southbridge.

Change-Id: Iabbaa4cd2fd367ed6decec7ef5cdcbae3b264d52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/654
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)

via/cx700: Move HAVE_HARD_RESET to northbridge

No in-tree cx700-using board has it not selected, so move
selection from boards to northbridge.

Change-Id: Ifa79954a48cf99b5f7e49960eafce805401e571c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/656
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

intel/82801dx: Move HAVE_HARD_RESET to southbridge

No in-tree 82801dx-using board has it not selected, so move
selection from boards to southbridge.

Change-Id: I69671cb6411a6cd9c791059ae9546dff3aff702c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/655
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Exit building if romstage.bin is larger than size of XIP

When the romstage.bin becomes bigger than the size of XIP, the
cbfstool can not allocate the romstage in the CBFS. But it doesn't
report an error. It will take quite a while to find out the root
cause.

Change-Id: I5be2a46a8b57934f14c5a0d4596f3bec4251e0aa
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/650
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Mainboard: Add AMD dinar mainboard.

Dinar mainboard is an AMD evaluation board for
Orochi Platform family15 model 00-0f processor.

The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets.
16 cores InterLagos Opteron processor are supported.
Windows 7 are verified on this platform.

Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/564
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

SIO: Add smsc sio1036 superio

Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/563
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

SIO: Add smsc/sch4037 superio support

Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/562
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

M4A785-M,M4A785T-M: fix SSDT tables

This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9
    (AMD Mahogany Fam10 ACPI table fixes.)

Change-Id: I9a9bf955de0a2a7accdbce8561b23596a8641af4
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/636
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>

M4A785T-M: fix TOM2.

This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9
(AMD Mahogany Fam10 ACPI table fixes.)

With commit permit to boot without pci=nocrs on the M4A785T-M board.

Before the fix dmesg contained the following:
  [    0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
  (20110112/psargs-359)
  [    0.480085] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
  (20110112/psargs-359)
  [    0.788222] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
  (20110112/psargs-359)

Now it only contains:
  [    0.312102] TOM: 0000000080000000 aka 2048M

Change-Id: I5d517604abe938af19b70d57d92c1f973114c1cd
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/635
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>

SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper

Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/561
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

AGESA F15: AGESA family15 model 00-0fh northbridge wrapper

Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/556
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

HWM: Nuvoton W83795G/ADG HWM support

Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans,
they are controled by a separate W83795G Hardware Monitor chip.
This patch adds Nuvoton W83795G/ADG HWM support.

Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/569
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Mainboard: Supermicro/h8qgi mainboard update

1. Supermicro H8QGI mainboard update to support both family10 Revison D
   processor and family15 model 00-0fh processor in one binary image.
2. RD890/SR56X0 IO hub CIMX wrapper support.
3. SP5100/SB700 southbridge CIMX wrapper support.

Both 8 cores and 16 Cores InterLagos Opteron Processor are
tested on this platform.
Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested.

Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/567
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

SIO: Winbond w83627dhg update

1. Stop include c file.
2. W83627dhg Pin 89, Pin 90 are multi function pins,
   add support to select them to I2C function.

Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/565
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

RD890: AMD RD890/SR56X0 CIMX wrapper

Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0,
RD890 and 990FX chipsets.

Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/559
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids

Change-Id: I13905f5730d08510c8f0f6e652f41a679d618d1b
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/609
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

AGESA F15: AGESA family15 model 00-0fh cpu wrapper

Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/555
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Intel cpus: use CPU_PHYSMASK_HI define in CAR

Unifies models 6ex, 6fx and 106cx.

Change-Id: I2bb632c7148a7d937f24eb559f7f4e539d227470
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/638
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Intel model_106cx: Use symbolic names for MTRR bits

Change-Id: I6ea5ca631c22fe870224a498b68d77d85798b3f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/637
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

AMD Geode cpus: apply un-written naming rules

Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.

Rename directories and Kconfig as follows:
   model_lx  -> geode_lx
   model_gx1 -> geode_gx1
   model_gx2 -> geode_gx2

Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/613
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: code cosmetics

Be consistend with coding style at least within a function -- don't mix
sizeof with plain values.

Change-Id: Iefb5b7fe4f54977f5505fc9cea65c9c4af3e7f3a
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/617
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Intel cpus: apply un-written naming rules

Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.

Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x.

Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/618
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: fix possible mem leak in get_option_as_string()

Change-Id: I7c3adbd1b72be81585bbaabb42532fc4cad57f58
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/616
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Remove non-existent include

Change-Id: I702d59371b4a57ce22623cbab6e936b653d57edf
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/619
Tested-by: build bot (Jenkins)

i5000: halt second BSP

If both FSBs on i5000 are equipped with CPU packages, one CPU
from each package is elected as BSP. To prevent races between
both BSPs, hlt the second BSP.

Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/615
Tested-by: build bot (Jenkins)

Add Intel Socket LGA771

Change-Id: Iee7d3ff2884d8c43ff1af498160589e551bc9cc8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/492
Tested-by: build bot (Jenkins)

VIA cpus: apply un-written naming rules

Rename files and directories:
  model_c3 -> c3
  model_c7 -> c7

Change-Id: If144fc501e8ae44b347ac44fa90c689c33a8e126
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/614
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Remove no-op Makefiles under mainboard directory

Patch removes following files:

    src/mainboard/amd/serengeti_cheetah/Makefile.inc
    src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc
    src/mainboard/broadcom/blast/Makefile.inc
    src/mainboard/hp/dl145_g1/Makefile.inc
    src/mainboard/msi/ms9282/Makefile.inc
    src/mainboard/supermicro/h8dme/Makefile.inc
    src/mainboard/tyan/s2881/Makefile.inc
    src/mainboard/tyan/s2892/Makefile.inc
    src/mainboard/via/epia-m700/Makefile.inc

Change-Id: I020776313abff1772be38afc896af51ca5ab6453
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/612
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

romcc: kill gcc warnings and .gitignore generated files

don't remove calls to `flatten()' and `correct_coalesce_conflicts()',
since they (probably) have side effects.

Change-Id: I78fc4163b3f5f1f5f3c5153f9559c22e11e8344d
Signed-off-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-on: http://review.coreboot.org/605
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Don't loop infinitely long on serial comm failures

If serial uart (8250/16x50) takes abnormally long to respond, give
up on logging to serial console and instead let the system boot.

Also reference bit in LSR register with correct name.

Change-Id: I3796efc3e8690425f04a130af4bc99541b64d335
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/611
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Delete hard-coded driver includes

Driver components are conditionally included in the build using the
Kconfig options.

Change-Id: I05417ee263a5b82e947600482dfb68f7a3f52d58
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/610
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: Remove workaround for bitfield management in EHCI driver

We don't use bitfields anymore.

Change-Id: I25ceec2024f659612871bcfe5f98df3a10789055
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/595
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

libpayload: Force checking all EHCI ports on power-on

EHCI port status reporting isn't very consistent on power-on,
so just looking for devices on all ports is the safest way to
find everything.

Change-Id: I26b4305016f0bed1d2c1b5cffc59d5813fa1cbbb
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/594
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Fix multipleVGA cards resource conflict on Windows

If multiple VGA-compatible legacy graphic cards decode the IO range
3B0-3BB, 3C0-3DF and MEM range A00000-BFFFF.
Windows 7 complain a resource conflict, so only one VGA card can
works at the same time.

There is a discussion in coreboot mail list before,
please reference thread: "how to prevent legacy resource conflictwith   multipleVGA cards"
http://www.coreboot.org/pipermail/coreboot/2010-October/061508.html

Linux using VGA Arbiter module(vgaarb) to resolve this resource conflict,
Please see the following linux dmesg log, more information can be found in
Linux source dir Documentation/vgaarbiter.txt.
But it seems that windows don't dealwith this conflict.
~# dmesg | grep -i vgaarb
[    0.774076] vgaarb: device added: PCI:0000:00:01.0,decodes=io+mem,owns=io+mem
[    0.776065] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=none,l
[    0.780051] vgaarb: loaded
[    0.784049] vgaarb: bridge control possible 0000:01:00.0
[    0.788050] vgaarb: bridge control possible 0000:00:01.0

For the second legacy graphic device, coreboot already disabled the
IO and MEM decode in function set_vga_bridge_bits().
But it will be enabled again in function pci_set_resource(),
if the second legacy vga-compatible graphic device take any IO/MEM resources.

Following log printed by enable_resources() shows the problem:
...snip...
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 subsystem <- 1022/1410
PCI: 00:01.0 cmd <- 07                <== The first graphic device
PCI: 00:01.1 subsystem <- 1022/1410
PCI: 00:01.1 cmd <- 02
PCI: 00:02.0 bridge ctrl <- 0003
PCI: 00:02.0 cmd <- 07
...snip...
PCI: 01:00.0 cmd <- 03                <== The second graphic device
PCI: 01:00.1 cmd <- 02
PCI: 02:00.0 cmd <- 02
PCI: 03:00.0 cmd <- 03
done.
...snip...

The IO & MEM decoding on the second vga graphic device should be disabled.
Please reference PCI spec. section 3.10 in detail.
set_vga_bridge_bits() would do this work for us, it did the right thing,
but was put to the wrong place, the setting would be overwritten by
assign_resources() later.

In order to make sure the set_vga_bridge_bits() setting not be
overwritten by others, moving the call of set_vga_bridge_bits()
to the end of dev_configure(), instead of at the beginning.

This patch resolved the dual graphic cards resource conflict in windows7,
multiple vga-compatible graphic cards can work together in windows7.

Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Change-Id: I0de5e3761b51e2723d9c1dc0c39fff692e3a779d
Reviewed-on: http://review.coreboot.org/489
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Inagua: Indent and wihtespace cleanup

Change-Id: Ie574e08f138c88084c8ce06d0d0acc489013e3d7
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/547
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>