/* Set Cache-as-RAM mask. */
movl $(MTRRphysMask_MSR(0)), %ecx
- movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
xorl %edx, %edx
wrmsr
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
- orl $(1 << 11), %eax
+ orl $MTRRdefTypeEn, %eax
wrmsr
/* Enable L2 cache. */
movl $MTRRphysMask_MSR(1), %ecx
xorl %edx, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
/* Disable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
- andl $(~(1 << 11)), %eax
+ andl $(~MTRRdefTypeEn), %eax
wrmsr
post_code(0x31)
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
- movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax
+ movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
xorl %edx, %edx
wrmsr
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
- orl $(1 << 11), %eax
+ orl $MTRRdefTypeEn, %eax
wrmsr
post_code(0x3b)