Force SB600 bootblock to use I/O for PCI config

If PCI config cycles use MMIO instead of I/O in the SB600 bootblock
code the cycles will go nowhere since the MMIO feature hasn't been
configured yet. This change forces the cycles to use I/O and
configures the southbridge decode range to what is defined by the
mainboards Kconfig.

Change-Id: I85297237f32f37b3fc1ff5b488cca0a43bcf20fd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/632
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c
index 70076227bffbe794b7041eff067b06988ad5f85e..45991ee540e237cd2eb03fb602518ac6d330f27c 100644 (file)
--- a/src/southbridge/amd/sb600/bootblock.c
+++ b/src/southbridge/amd/sb600/bootblock.c
@@ -37,19 +37,19 @@ static void sb600_enable_rom(void)
        u8 reg8;
        device_t dev;
 
-       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
-                                      PCI_DEVICE_ID_ATI_SB600_LPC), 0);
+       dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
+                       PCI_DEVICE_ID_ATI_SB600_LPC), 0);
 
        /* Decode variable LPC ROM address ranges 1 and 2. */
-       reg8 = pci_read_config8(dev, 0x48);
+       reg8 = pci_io_read_config8(dev, 0x48);
        reg8 |= (1 << 3) | (1 << 4);
-       pci_write_config8(dev, 0x48, reg8);
+       pci_io_write_config8(dev, 0x48, reg8);
 
        /* LPC ROM address range 1: */
        /* Enable LPC ROM range mirroring start at 0x000e(0000). */
-       pci_write_config16(dev, 0x68, 0x000e);
+       pci_io_write_config16(dev, 0x68, 0x000e);
        /* Enable LPC ROM range mirroring end at 0x000f(ffff). */
-       pci_write_config16(dev, 0x6a, 0x000f);
+       pci_io_write_config16(dev, 0x6a, 0x000f);
 
        /* LPC ROM address range 2: */
        /*
@@ -59,9 +59,9 @@ static void sb600_enable_rom(void)
         * 0xffe0(0000): 2MB
         * 0xffc0(0000): 4MB
         */
-       pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
+       pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* 4 MB */
        /* Enable LPC ROM range end at 0xffff(ffff). */
-       pci_write_config16(dev, 0x6e, 0xffff);
+       pci_io_write_config16(dev, 0x6e, 0xffff);
 }
 
 static void bootblock_southbridge_init(void)