Fix ECC disable option for AMD Fam10 DDR2 and DDR3.

The logic was backwards on the ECC enable/disable option. Also added better
debug output when the debug RAM init feature is enabled.

Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/670
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 5abe6d04ddb1a42440f50ee4d776b34355eab1ba..36b473a55fdd921c5aa23a27bdf809f0432fb270 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -300,7 +300,7 @@ restartinit:
        }
 
        mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) );     // Node 0
-       print_t("All Done\n");
+       print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus);
        return;
 
 fatalexit:

diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c
index 87ac3acf3687bf0584a5c03c3d2fff6aaf2351ed..58e61ae0ee6a66c0c4a4fbe3e2b20d626efaf766 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c
@@ -115,7 +115,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
 
        AllECC = 1;
        MemClrECC = 0;
-       print_t(" ECCInit 0 \n");
        for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
                struct DCTStatStruc *pDCTstat;
                pDCTstat = pDCTstatA + Node;
@@ -133,7 +132,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
                                        LDramECC = isDramECCEn_D(pDCTstat);
                                        if(pDCTstat->ErrCode != SC_RunningOK) {
                                                pDCTstat->Status &=  ~(1 << SB_ECCDIMMs);
-                                               if (OB_NBECC) {
+                                               if (!OB_NBECC) {
                                                        pDCTstat->ErrStatus |= (1 << SB_DramECCDis);
                                                }
                                                AllECC = 0;
@@ -164,15 +163,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
                        }
                }       /* if Node present */
        }
-       print_t(" ECCInit 1 \n");
 
        if(AllECC)
                pMCTstat->GStatus |= 1<<GSB_ECCDIMMs;
        else
                pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs);
 
-       print_t(" ECCInit 2 \n");
-
        /* Program the Dram BKScrub CTL to the proper (user selected) value.*/
        /* Reset MC4_STS. */
        for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
@@ -212,12 +208,22 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
                        }       /*Node has Dram */
                }       /*if Node present */
        }
-       print_t(" ECCInit 3 \n");
 
        if(mctGet_NVbits(NV_SyncOnUnEccEn))
                setSyncOnUnEccEn_D(pMCTstat, pDCTstatA);
 
        mctHookAfterECC();
+       for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
+               struct DCTStatStruc *pDCTstat;
+               pDCTstat = pDCTstatA + Node;
+               if (NodePresent_D(Node)) {
+                       print_tx("ECCInit: Node ", Node);
+                       print_tx("ECCInit: Status ", pDCTstat->Status);
+                       print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus);
+                       print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode);
+                       print_t("ECCInit: Done\n");
+               }
+       }
        return MemClrECC;
 }
 

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 1faed5a2e96f64673df5ecfb4d13dbddd0f0c2df..d126a95105738b6a110af865d743182ddee21390 100644 (file)
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -343,7 +343,7 @@ restartinit:
        }
 
        mct_FinalMCT_D(pMCTstat, pDCTstatA);
-       printk(BIOS_DEBUG, "All Done\n");
+       printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus);
        return;
 
 fatalexit:

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index ca03f4b5ac5d02da44e67ca0318be90f1dddae1b..6107e80d25dfd5bbe4e4c2cf9a39626047c1d991 100644 (file)
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -127,7 +127,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
                                        LDramECC = isDramECCEn_D(pDCTstat);
                                        if(pDCTstat->ErrCode != SC_RunningOK) {
                                                pDCTstat->Status &=  ~(1 << SB_ECCDIMMs);
-                                               if (OB_NBECC) {
+                                               if (!OB_NBECC) {
                                                        pDCTstat->ErrStatus |= (1 << SB_DramECCDis);
                                                }
                                                AllECC = 0;
@@ -146,6 +146,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
                                                Set_NB32(dev, reg, val);
                                                DCTMemClr_Init_D(pMCTstat, pDCTstat);
                                                MemClrECC = 1;
+                                               printk(BIOS_DEBUG, "  ECC enabled on node: %02x\n", Node);
                                        }
                                }       /* this node has ECC enabled dram */
                        } else {
@@ -207,6 +208,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
                setSyncOnUnEccEn_D(pMCTstat, pDCTstatA);
 
        mctHookAfterECC();
+       for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
+               struct DCTStatStruc *pDCTstat;
+               pDCTstat = pDCTstatA + Node;
+               if (NodePresent_D(Node)) {
+                       printk(BIOS_DEBUG, "ECCInit: Node %02x\n", Node);
+                       printk(BIOS_DEBUG, "ECCInit: Status %x\n", pDCTstat->Status);
+                       printk(BIOS_DEBUG, "ECCInit: ErrStatus %x\n", pDCTstat->ErrStatus);
+                       printk(BIOS_DEBUG, "ECCInit: ErrCode %x\n", pDCTstat->ErrCode);
+                       printk(BIOS_DEBUG, "ECCInit: Done\n");
+               }
+       }
        return MemClrECC;
 }