bool
config SUPERIO_SMSC_SMSCSUPERIO
bool
+config SUPERIO_SMSC_SIO1036
+ bool
config SUPERIO_SMSC_SCH4037
bool
subdirs-y += sio10n268
subdirs-y += kbc1100
subdirs-y += smscsuperio
+subdirs-y += sio1036
subdirs-y += sch4037
--- /dev/null
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_SMSC_SIO1036_CHIP_H
+#define SUPERIO_SMSC_SIO1036_CHIP_H
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct chip_operations;
+extern struct chip_operations superio_smsc_kbc1100_ops;
+
+struct superio_smsc_sio1036_config {
+ struct uart8250 com1;
+};
+
+#endif //SUPERIO_SMSC_SIO1036_CHIP_H
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define SIO1036_SP1 0 /* Com1 */
+
+#define UART_POWER_DOWN (1 << 7)
+#define LPT_POWER_DOWN (1 << 2)
+#define IR_OUPUT_MUX (1 << 6)
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
+
+#include <arch/romcc_io.h>
+#include "sio1036.h"
+
+#ifndef CONFIG_TTYS0_BASE
+#define CONFIG_TTYS0_BASE 0x3F8
+#endif
+static inline void sio1036_enter_conf_state(device_t dev)
+{
+ unsigned port = dev>>8;
+ outb(0x55, port);
+}
+
+static inline void sio1036_exit_conf_state(device_t dev)
+{
+ unsigned port = dev>>8;
+ outb(0xaa, port);
+}
+
+static u8 detect_sio1036_chip(unsigned port)
+{
+ device_t dev;
+ dev = PNP_DEV (port, SIO1036_SP1);
+ unsigned data;
+ sio1036_enter_conf_state (dev);
+ data = pnp_read_config (dev, 0x0D);
+ sio1036_exit_conf_state(dev);
+ /* detect smsc sio1036 chip */
+ if (data == 0x82) {
+ /* Found SMSC SIO1036 chip */
+ return 0;
+ }
+ else {
+ return -1;
+ };
+}
+
+static inline void sio1036_early_init(unsigned port)
+{
+ device_t dev;
+ dev = PNP_DEV (port, SIO1036_SP1);
+
+ if (detect_sio1036_chip(port) != 0) {
+ /* Not found SMSC SIO1036 */
+ return;
+ }
+ sio1036_enter_conf_state (dev);
+
+ /* Enable SMSC UART 0 */
+ /* Valid configuration cycle */
+ pnp_write_config (dev, 0x00, 0x28);
+
+ /* PP power/mode/cr lock */
+ pnp_write_config (dev, 0x01, 0x98 | LPT_POWER_DOWN);
+ pnp_write_config (dev, 0x02, 0x08 | UART_POWER_DOWN);
+
+ /*Auto power management*/
+ pnp_write_config (dev, 0x07, 0x00 );
+
+ /*ECP FIFO threhod */
+ pnp_write_config (dev, 0x0A, 0x00 | IR_OUPUT_MUX);
+
+ /*GPIO direction register 2 */
+ pnp_write_config (dev, 0x033, 0x00);
+
+ /*UART Mode */
+ pnp_write_config (dev, 0x0C, 0x02);
+
+ /* GPIO polarity regisgter 2 */
+ pnp_write_config (dev, 0x034, 0x00);
+
+ /* Enable SMSC UART 0 */
+ /*Set base io address */
+ pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2));
+
+ /* Set UART IRQ onto 0x04 */
+ pnp_write_config (dev, 0x28, 0x04);
+
+ sio1036_exit_conf_state(dev);
+}
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* RAM driver for the SMSC SIO1036 Super I/O chip */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "sio1036.h"
+
+/* Forward declarations */
+static void enable_dev(device_t dev);
+static void sio1036_pnp_set_resources(device_t dev);
+static void sio1036_pnp_enable_resources(device_t dev);
+static void sio1036_pnp_enable(device_t dev);
+static void sio1036_init(device_t dev);
+
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+
+struct chip_operations superio_smsc_sio1036_ops = {
+ CHIP_NAME("SMSC SIO1036 Super I/O")
+ .enable_dev = enable_dev
+};
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = sio1036_pnp_set_resources,
+ .enable_resources = sio1036_pnp_enable_resources,
+ .enable = sio1036_pnp_enable,
+ .init = sio1036_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ {},
+};
+
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+static void sio1036_pnp_set_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_resources(dev);
+ pnp_exit_conf_state(dev);
+}
+
+static void sio1036_pnp_enable_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_enable_resources(dev);
+ pnp_exit_conf_state(dev);
+}
+
+static void sio1036_pnp_enable(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+
+ if(dev->enabled) {
+ pnp_set_enable(dev, 1);
+ }
+ else {
+ pnp_set_enable(dev, 0);
+ }
+ pnp_exit_conf_state(dev);
+}
+
+static void sio1036_init(device_t dev)
+{
+ struct superio_smsc_sio1036_config *conf = dev->chip_info;
+ struct resource *res0, *res1;
+
+
+
+ if (!dev->enabled) {
+ return;
+ }
+
+ switch(dev->path.pnp.device) {
+
+ default:
+ break;
+ }
+}
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ outb(0x55, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ outb(0xaa, dev->path.pnp.port);
+}
+
projects / coreboot.git / commitdiff