Warren Turkal [Fri, 3 Sep 2010 09:31:13 +0000 (09:31 +0000)]
Add DMIBAR support for Intel X58 southbridge
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5770
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Warren Turkal [Fri, 3 Sep 2010 08:57:32 +0000 (08:57 +0000)]
Add convenience rules for cscope to Makefile.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5769
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 3 Sep 2010 08:53:06 +0000 (08:53 +0000)]
The current workaround for binutils on mingw (or any non texinfo system) failed.
While we're at it, improve DESTDIR handling
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5768
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Thu, 2 Sep 2010 22:02:53 +0000 (22:02 +0000)]
Fix compilation for mtarvon. CAR initialization does early_mtrr_init,
jarell/debug.c isn't ready for gcc, and skip_romstage() doesn't compile.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5767
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Thu, 2 Sep 2010 20:30:31 +0000 (20:30 +0000)]
Trivial warning fix for adl855pc.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5766
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Thu, 2 Sep 2010 18:36:29 +0000 (18:36 +0000)]
Fix abuild to build all boards. Revision 5754 changed the way vendors and
boards were specified in Kconfig, and abuild depended on that. Since that rev
it has only built qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5765
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Thu, 2 Sep 2010 18:29:31 +0000 (18:29 +0000)]
Revert 5762. It silently broke a lot of boards because abuild was broken.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5764
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Wed, 1 Sep 2010 21:03:03 +0000 (21:03 +0000)]
Simplify last_dev_p so that it matches comments.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5763
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Wed, 1 Sep 2010 16:27:13 +0000 (16:27 +0000)]
Fix race condition in option_table.h generation by moving the include statement
to those files that actually need it. This significantly reduces the number of
dependencies, so it's no longer extremely ugly to specify them manually (see
the src/pc80/Makefile.inc portion)
Also, drop the AMD DBM690T work around for the issue.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5762
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Warren Turkal [Wed, 1 Sep 2010 03:40:57 +0000 (03:40 +0000)]
Add support for dumping GPIOS on Intel ICH10R. This information comes from the Intel ICH10 Family Datasheet.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5761
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Tue, 31 Aug 2010 19:19:16 +0000 (19:19 +0000)]
SMC_CONFIG is needed before the device tree is ready and some people
would rather not have mainboard settings like sio_gp1x_config in the
device tree anyway. So found a nice united home for both in Kconfig,
where users can change them without having to mess around in the C code.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5760
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Tue, 31 Aug 2010 19:02:45 +0000 (19:02 +0000)]
Make ALIX.2D3 support 2D2 as well.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5759
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Tue, 31 Aug 2010 06:10:54 +0000 (06:10 +0000)]
Get Byte65/66 for register manufacture ID code. RegMan1Present will
be used in write levelization training.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5758
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Mon, 30 Aug 2010 21:52:38 +0000 (21:52 +0000)]
Make yabel work for non-zero bus numbers. The link_num is not the bus number.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5757
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 30 Aug 2010 17:53:13 +0000 (17:53 +0000)]
We call this cache as ram everywhere, so let's call it the same in Kconfig
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 30 Aug 2010 16:52:48 +0000 (16:52 +0000)]
Fix intel mtarvon compilation by switching it over to CAR.
This should be unproblematic, as there are other boards with the same "socket"
that work with CAR already. Tests are highly appreciated though!
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5755
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Mon, 30 Aug 2010 16:36:51 +0000 (16:36 +0000)]
Restructured all vendors' Kconfig files to no longer source the boards'
Kconfigs from within the choice/endchoice block. This makes it possible to
define user visible board specific options. Moved all vendor names and PCI
ids to the vendors' Kconfigs. Now all options in each file depend on the same
symbol, so replaced all "depends on"s with a single "if". Sorted boards
(sort -d), cleaned whitespace.
This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is
always "y" and never used. It it simply needed to have something to attach
the boards' "select" statements to.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Andreas Schultz [Mon, 30 Aug 2010 16:32:23 +0000 (16:32 +0000)]
This file was missing from r5751.
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5753
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Andreas Schultz [Mon, 30 Aug 2010 16:22:22 +0000 (16:22 +0000)]
Support for Lanner EM-8510 Board
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
---
src/mainboard/Kconfig | 8 ++
src/mainboard/lanner/Kconfig | 8 ++
src/mainboard/lanner/em8510/Kconfig | 38 +++++++++++
src/mainboard/lanner/em8510/Makefile.inc | 21 ++++++
src/mainboard/lanner/em8510/chip.h | 23 +++++++
src/mainboard/lanner/em8510/cmos.layout | 74 +++++++++++++++++++++
src/mainboard/lanner/em8510/devicetree.cb | 60 +++++++++++++++++
src/mainboard/lanner/em8510/irq_tables.c | 56 ++++++++++++++++
src/mainboard/lanner/em8510/mainboard.c | 27 ++++++++
src/mainboard/lanner/em8510/romstage.c | 103 +++++++++++++++++++++++++++++
10 files changed, 418 insertions(+), 0 deletions(-)
create mode 100644 src/mainboard/lanner/Kconfig
create mode 100644 src/mainboard/lanner/em8510/Kconfig
create mode 100644 src/mainboard/lanner/em8510/Makefile.inc
create mode 100644 src/mainboard/lanner/em8510/chip.h
create mode 100644 src/mainboard/lanner/em8510/cmos.layout
create mode 100644 src/mainboard/lanner/em8510/devicetree.cb
create mode 100644 src/mainboard/lanner/em8510/irq_tables.c
create mode 100644 src/mainboard/lanner/em8510/mainboard.c
create mode 100644 src/mainboard/lanner/em8510/romstage.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5752
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Andreas Schultz [Mon, 30 Aug 2010 16:19:04 +0000 (16:19 +0000)]
Rework i855GM/i855GME support
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
---
src/northbridge/intel/i855/Kconfig | 30 +
src/northbridge/intel/i855/i855.h | 76 +++
src/northbridge/intel/i855/northbridge.c | 21 +
src/northbridge/intel/i855/raminit.c | 1036 +++++++++++++++++++++++++-----
src/northbridge/intel/i855/raminit.h | 14 +-
5 files changed, 1002 insertions(+), 175 deletions(-)
create mode 100644 src/northbridge/intel/i855/i855.h
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5751
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Andreas Schultz [Mon, 30 Aug 2010 16:16:01 +0000 (16:16 +0000)]
mPGA479M Sockets can take Intel Mobile Celeron.
The 1.2GHz model has CPUID F29. This adds them to the list of CPUs for that socket.
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
This patch likely breaks the following two boards since it unconditionally
activates CAR code for this socket:
* digitallogic/adl855pc
* intel/mtarvon
stepan suggests moving those two boards over to CAR, too, so we don't have to
worry.
---
src/cpu/intel/socket_mPGA479M/Kconfig | 1 +
src/cpu/intel/socket_mPGA479M/Makefile.inc | 2 ++
2 files changed, 3 insertions(+), 0 deletions(-)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5750
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Mon, 30 Aug 2010 09:40:41 +0000 (09:40 +0000)]
Multi-DIMMS on AMD ddr2 MCT channel B fixed.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5749
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Mon, 30 Aug 2010 07:31:31 +0000 (07:31 +0000)]
Multi-DIMMS on AMD ddr3 MCT channel B works.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5748
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Mon, 30 Aug 2010 07:24:13 +0000 (07:24 +0000)]
Trivial syntax correction of AMD mct_ddr3 dir.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Kerry She <Kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5747
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sat, 28 Aug 2010 23:23:47 +0000 (23:23 +0000)]
fix compilation of hello.elf example payload.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5746
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Fri, 27 Aug 2010 09:36:41 +0000 (09:36 +0000)]
drop three unneeded config variables:
- HAVE_HIGH_TABLES
- HAVE_LOW_TABLES
- FALLBACK_SIZE
Jens Rottmann sent an almost identical patch at the same time, so
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Thu, 26 Aug 2010 18:24:04 +0000 (18:24 +0000)]
Remove unused mainboard_config definitions. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5744
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Thu, 26 Aug 2010 12:46:02 +0000 (12:46 +0000)]
CONFIG_DEBUG_RAM_SETUP and CONFIG_DEBUG_SMBUS are only available if the board /
chipset support it. But this involves a long list of 'depends', which you have
to remember updating manually. Converted this into HAVE_... properties, which
will be inherited automatically if someone copies a chipset to create a new
one.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Thu, 26 Aug 2010 12:43:58 +0000 (12:43 +0000)]
One of my boards needs this mini delay in order to survive ram initialization.
Odd. The others don't.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5742
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Thu, 26 Aug 2010 12:42:43 +0000 (12:42 +0000)]
kontron 986lcd-m: Fix compilation if there is no oprom execution at all...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5741
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Wed, 25 Aug 2010 18:35:42 +0000 (18:35 +0000)]
Fix i945 based boards
- prevent GCC from inlining do_ram_command - it will break RAM initialization.
- fix the PCIRST# mechanism in those boards that do it, it requires 200ms, not
200us
- move PCIRST# as early as possible (before ich7_enable_lpc)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5740
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Aurelien Guillaume [Tue, 24 Aug 2010 12:58:17 +0000 (12:58 +0000)]
* Adds support for PC Engines Alix.2D(1)3 board to Coreboot.
* DRAM initialization done message is now printed in debug-mode only, rather than everytime.
Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5739
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 23 Aug 2010 18:43:27 +0000 (18:43 +0000)]
mark unused variables in x86emu as unused. gcc has a mechanism for this.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5738
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Sun, 22 Aug 2010 20:02:27 +0000 (20:02 +0000)]
Fix up some copyrights
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5737
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 20:00:42 +0000 (20:00 +0000)]
I've checked Revision Guide for AMD Family10h processors (#41322) rev
3.74 June 2010 for errata 351 and it agrees with the comment on
setting ForceFullT0= 000b but I believe the code didn't honor the
comment.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5736
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:59:27 +0000 (19:59 +0000)]
RB_C3 should also apply the workaround for errata 354, according to
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5735
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:56:47 +0000 (19:56 +0000)]
RB_C3 and HY-D0 should also apply the workaround for errata 344, according to
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
My processor wasn't getting the workaround
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5734
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:54:26 +0000 (19:54 +0000)]
documented workaround erratum 414, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
with patch.erratum414 it stops here (next patches don't make it get further,
but they're needed according to documentation, don't break anything for me and
I still don't have a solution for booting, so I'm keeping them there in case
they fix something.
testx =
5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx =
5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading stage image.
Check CBFS header at
fffffd2e
magic is
4f524243
Found CBFS header at
fffffd2e
Check fallback/romstage
CBFS: follow chain:
fff00000 + 38 + 15b41 + align ->
fff15b80
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x200000 (
1114112 bytes), entry @
0x20000
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5733
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:51:34 +0000 (19:51 +0000)]
documented workaround erratum 372, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
with this one it stops here or earlier (as soon as before the patch,
sometimes):
*** Yes, the copy/decompress is taking a while, FIXME!
v_esp=
000cbf48
testx =
5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx =
5a5a5a5a
Disabling cache as ram now
Clearing initial memory region:
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5732
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:49:46 +0000 (19:49 +0000)]
Complete code for errata 343. Revision Guide for AMD Family10h
processors (#41322) rev 3.74 June 2010 says to set the register
to 1 before CAR and to 0 after. We were setting it to 0 after CAR,
but not to 1 before.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5731
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:48:29 +0000 (19:48 +0000)]
Include RB_C3 in erratum 346
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5730
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:45:57 +0000 (19:45 +0000)]
Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc.
While reviewing impact of this change it seems code for erratum 531 was not in
sync with current docs. I have checked uses of AMD_FAM10_ALL, but I
haven't looked up the docs for all of them, at first sight it seems ok
to include all FAM10 revisions in this mask.
Apply errata 531 only to revisions listed in Revision Guide for AMD Family10h
processors (#41322) rev 3.74 June 2010. Before it was applied also to
DR-B0, DA-C3 or HY-D0 which are not affected according to current docs.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5729
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Anders Juel Jensen [Sun, 22 Aug 2010 19:41:47 +0000 (19:41 +0000)]
Add suport for normal register dumping on ite8510E/TE/G
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5728
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Anders Juel Jensen [Sun, 22 Aug 2010 19:40:58 +0000 (19:40 +0000)]
Add another port to find ite8510 on.
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5727
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Anders Juel Jensen [Sun, 22 Aug 2010 19:40:11 +0000 (19:40 +0000)]
Add support for non LDN register/device naming.
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5726
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Anders Juel Jensen [Sun, 22 Aug 2010 19:39:04 +0000 (19:39 +0000)]
The LDFLAGS = -lz is needed to compile on slackware.
Clubbering CFLAGS is never a good idea.
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5725
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Fri, 20 Aug 2010 20:45:04 +0000 (20:45 +0000)]
Remove a couple of warnings. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5724
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Oskar Enoksson [Fri, 20 Aug 2010 20:37:27 +0000 (20:37 +0000)]
Add support for the HP DL145 G1, based on the Tyan s2881.
Signed-off-by: Oskar Enoksson <oskeno@foi.se>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5723
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Wed, 18 Aug 2010 21:23:27 +0000 (21:23 +0000)]
libpayload: fix garbage on screen with Geode-LX VGA
Clear initial garbage in VGA memory and fix scroll_up, which scrolled 1 scanline
instead of 1 text line by mistake.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5722
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Wed, 18 Aug 2010 01:55:11 +0000 (01:55 +0000)]
The attached file add pa78vm5 dev3 detection function to avoid the building error.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5721
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Rudolf Marek [Tue, 17 Aug 2010 21:03:17 +0000 (21:03 +0000)]
Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and
I removed the gpio asserts - I think those are not used here.
The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better.
The classic PCI slot works fine too. However it seems SATA has some issues.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5720
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Tue, 17 Aug 2010 16:32:42 +0000 (16:32 +0000)]
Correct for size_t would be %zx, but coreboot's printf doesn't support this.
Trying to keep it simple: Two sizes are expected equal so use same %x for both.
Cast to unsigned int to make sure it fits.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5719
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Tue, 17 Aug 2010 15:19:32 +0000 (15:19 +0000)]
Commit (non-working!) Jetway PA78VM5 mainboard
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5718
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Tue, 17 Aug 2010 15:05:05 +0000 (15:05 +0000)]
Support for Fintek F71863FG. This might need some work on the copyright
notices. Getting it into the tree so people can get to it.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5717
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marc Bertens [Tue, 17 Aug 2010 11:32:21 +0000 (11:32 +0000)]
image parsing for getpir
when adding for example build/coreboot_ram as parameter
it looks in the file for the PIRQ table prints it to stdout
and shows if the checksum is correct.
getpir works as before without any commandline parameters.
This is very handy for developing a PIRQ table.
Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5716
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Tue, 17 Aug 2010 11:22:40 +0000 (11:22 +0000)]
Another AMD 780/700 mainboard: Gigabyte MA78GM-US2H
http://www.gigabyte.cn/products/product-page.aspx?pid=3118#ov
the simple config is
AM2+DDR2+SB700+RS780, the superIO is IT8718F
The patch has been tested with SeaBIOS + SUSE11.2
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5715
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Tue, 17 Aug 2010 11:11:09 +0000 (11:11 +0000)]
Tilapila supports both dual slot and single slot. The difference should be
detected by the existence of dev3. Some other RS780 mainboard has
the same function. The patch added the function to make these boards work
smoothly.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5714
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Tue, 17 Aug 2010 11:08:31 +0000 (11:08 +0000)]
Add support for Gigabyte MA785GMT mainboard.
Details of the hardware configuration can be found at
http://www.gigabyte.com/products/product-page.aspx?pid=3478
Brief configuration is:
1. CPU:Support for AM3 processors: AMD PhenomTM II processor/ AMD Athlon™ II processor
2. North Bridge: AMD 785G
3. South Bridge: AMD SB710
4: Super IO : ITE8718F
The mainboard has two bios flashchip. Coreboot ROM should be flashed into the
M_BIOS (which means main bios).
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5713
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Tue, 17 Aug 2010 10:54:36 +0000 (10:54 +0000)]
fix nokia ip530 Kconfig, missed on last check-in
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5712
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Tue, 17 Aug 2010 10:14:50 +0000 (10:14 +0000)]
libpayload: Add function to fix CMOS checksum.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5711
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Tue, 17 Aug 2010 09:52:01 +0000 (09:52 +0000)]
Whatever happened here,... The DEC Tulip is a network card, no bridge of any
kind. Move it to drivers and make the necessary adaptions. Also drop empty
drivers/generic/generic and start cleaning up Makefiles in drivers/
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5710
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Corey Osgood [Tue, 17 Aug 2010 08:33:44 +0000 (08:33 +0000)]
Add support for the Intel NM10 (a variant of ICH7) and ICH8 southbridges.
Both are tested and appear to be working, however I'm not 100% clear
on if the NM10 has any other PCI IDs.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5709
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Tue, 17 Aug 2010 08:24:01 +0000 (08:24 +0000)]
Add support for Fintek
F81216D/DG/AD
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5708
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Tue, 17 Aug 2010 07:46:50 +0000 (07:46 +0000)]
Clarify comment a bit
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5707
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Corey Osgood [Tue, 17 Aug 2010 07:14:44 +0000 (07:14 +0000)]
Add support for the Nuvoton NCT5571D. This chip acts nothing like the other
supported Nuvoton chip, but identical to a Winbond, and Nuvoton is a subsidary
of Winbond, so for simplicity's sake I've added it to the Winbond file.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5706
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Rudolf Marek [Tue, 17 Aug 2010 06:18:47 +0000 (06:18 +0000)]
Look for actual framebuffer size instead of hardcoding UMA
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5705
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Tue, 17 Aug 2010 06:12:59 +0000 (06:12 +0000)]
Fix warnings (that become errors) in AMDHT for certain configurations (unused functions)
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5704
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Tue, 17 Aug 2010 02:14:53 +0000 (02:14 +0000)]
Feature of lane reversal of AMD RS780 is tested.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5703
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Mon, 16 Aug 2010 20:00:49 +0000 (20:00 +0000)]
White space changes for s2881 device tree.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5702
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 16 Aug 2010 18:21:56 +0000 (18:21 +0000)]
sconfig parser:
- print erroneous string in error message
- print line numbers starting from 1 instead of 0
- exit with return code 1 on errors
- check return values of fopen operations
- only create output file if input file was parsed without errors
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5701
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Mon, 16 Aug 2010 18:04:13 +0000 (18:04 +0000)]
Fix strcmp and strncmp. They failed in several important scenarios
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5700
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Mon, 16 Aug 2010 17:51:47 +0000 (17:51 +0000)]
Add #define that states the libpci interface version we implement
(flashrom needs it)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5699
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Mon, 16 Aug 2010 16:25:23 +0000 (16:25 +0000)]
Call mainboard init functions.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5698
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Sun, 15 Aug 2010 11:37:41 +0000 (11:37 +0000)]
Gigabyte dual bios mainboard will always reboot, caused by the superio.
After lots of testing, the SuperIO LDN 7, register 0xEF is the key to the
problem. This patch adds a function which stops dual bios mainboards from
rebooting, when called.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5697
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sat, 14 Aug 2010 20:38:17 +0000 (20:38 +0000)]
My forgotten CAR cleanup patch...
- Drop lots of dead code from the various cache_as_ram.inc files.
- Use some descriptive macros instead of magic numbers for MTRR MSRs
- drop unused duplicate descriptors from romstage GDT
- slightly reformatting code and comments
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5696
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sat, 14 Aug 2010 17:45:54 +0000 (17:45 +0000)]
My old mcp55 azalia fix from May 2010. Was never checked in.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5695
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sat, 14 Aug 2010 17:31:49 +0000 (17:31 +0000)]
bootblock_prologue.c (not a .c file!) and i386/init/crt0_prologue.inc were
pretty much 1:1 the same file (despite an include and a typo) so drop one
instance of it. We only have one prologue.inc for the romstage code now.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5694
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sat, 14 Aug 2010 17:27:27 +0000 (17:27 +0000)]
clean up comment in entry32.inc
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5693
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Fri, 13 Aug 2010 15:42:09 +0000 (15:42 +0000)]
Build 8151 for s2885. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5692
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 13 Aug 2010 09:18:58 +0000 (09:18 +0000)]
Add support for OHCI controllers and prelimiary support for xHCI (USB3) controllers.
Improve scanning for USB controllers.
Limitations:
- OHCI doesn't support interrupt transfers yet (ie. no keyboards)
- xHCI just does initialization and device attach/detach so far
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5691
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Donald Huang [Tue, 10 Aug 2010 23:34:51 +0000 (23:34 +0000)]
Superiotool support for the IT8500 embedded controller.
Signed-off-by: Donald Huang <donald.huang@ite.com.tw>
Signed-off-by: Yung-chieh Lo <yjlou@google.com>
Signed-off-by: David Hendricks <dhendrix@google.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5690
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
David Hendricks [Mon, 9 Aug 2010 23:13:13 +0000 (23:13 +0000)]
Some chips do not require enter/exit sequences. This causes them to be
detected and printed multiple times in probe_idregs_* functions where a
simple series of enter --> probe/print --> exit calls are made.
This patch adds a simple check after each set of those calls to make the
functions quit after a chip is found.
Signed-off-by: David Hendricks <dhendrix@google.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5689
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 9 Aug 2010 13:28:18 +0000 (13:28 +0000)]
make sconfig parser regeneration menu selectable
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5688
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Mon, 9 Aug 2010 12:58:16 +0000 (12:58 +0000)]
Fix build error introduced in r5868.
aliased_name was a compatibility hack to match the output of the C rewrite
with the python version's results. It seems that we carried these
useless symbols with us for years, just without any impact good or bad.
By declaring devices static and tightening the screws (-Werror), the
compiler now knows that these declarations are useless - and stops.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5687
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 9 Aug 2010 12:02:00 +0000 (12:02 +0000)]
non-root devices are not supposed to be accessed outside of static.c except by
walking the tree.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5686
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Thu, 5 Aug 2010 14:41:29 +0000 (14:41 +0000)]
Change default path and configuration for Coreinfo.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Cai Bai Yin <caibaiyin.pku@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5685
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 5 Aug 2010 06:12:16 +0000 (06:12 +0000)]
The number of cores is got by reading the bit 15,13,12 of [0,24,3,e8].
The bit 15 seems to be a new feature when CPU started to have more than 4
cores.
Zheng
Yes, this was add for revD.
Marc Jones
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5684
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Wed, 4 Aug 2010 19:29:11 +0000 (19:29 +0000)]
Remove warnings from USB debug console code.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5683
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Tue, 3 Aug 2010 15:42:29 +0000 (15:42 +0000)]
Drop the USE_PRINTK_IN_CAR option. It's a bogus decision to make for any user /
board porter: printk should always be available in CAR mode.
Also drop CONFIG_USE_INIT, it's only been selected on one ASROCK board
but it's not been used there. Very odd.
There is one usage of CONFIG_USE_INIT which was always off in
src/cpu/intel/car/cache_as_ram.inc and we have to figure out what to do with
those few lines.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5682
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Myles Watson [Tue, 3 Aug 2010 15:01:39 +0000 (15:01 +0000)]
VGA code needs to be refactored before it can be compiled conditionally.
Revert until someone with the boards refactors it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5681
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Myles Watson [Mon, 2 Aug 2010 15:14:13 +0000 (15:14 +0000)]
Build VGA code conditionally to avoid errors when using SeaBIOS.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5680
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Mattias Mattsson [Mon, 2 Aug 2010 02:34:20 +0000 (02:34 +0000)]
Adds id for ITE IT8707F to superiotool.
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5679
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Stefan Reinauer [Sun, 1 Aug 2010 17:22:17 +0000 (17:22 +0000)]
make early_mtrr_init() invisible for cache as ram targets as it breaks them.
Fix up converted mainboards that still used early_mtrr_init()
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5678
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Corey Osgood [Sun, 1 Aug 2010 17:20:20 +0000 (17:20 +0000)]
Clarify a comment on an old hack, remove the call to early_mtrr_init
that causes CAR to hang, provide more debugging output wrt memory size,
and correct the numbering on the ram init sequence.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5677
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Stefan Reinauer [Sun, 1 Aug 2010 15:41:14 +0000 (15:41 +0000)]
- fix SMM code relocation race
- make SMM relocation debugging Kconfig accessible
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5676
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Björn Busse [Sun, 1 Aug 2010 15:33:30 +0000 (15:33 +0000)]
add i945GSE to inteltool
Signed-off-by: Björn Busse <bj.rn@co-assembler.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5675
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Corey Osgood [Sun, 1 Aug 2010 02:33:42 +0000 (02:33 +0000)]
Update my old, no longer active email addresses
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5674
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Corey Osgood [Thu, 29 Jul 2010 19:25:31 +0000 (19:25 +0000)]
Add support for the Intel Atom D400/500- and N400-series integrated
northbridge. Also add support for the very similar Q963/965 northbridge.
Tested:
D510: confirmed working, with MCHBAR enable code
Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work
Untested:
D410/D525/N400: should be the same northbridge
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5673
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Cai Bai Yin [Thu, 29 Jul 2010 00:08:21 +0000 (00:08 +0000)]
Resolved the bug of filo+libpayload building. The bug is if libpayload is installed before filo load "make -C ../libpayload/Makefile DEST=**", it would not
install correctly. Also, distclean removes .xcompile now.
Signed-off-by: Cai Bai Yin <caibaiyin.pku@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5672
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Nils Jacobs [Wed, 28 Jul 2010 00:27:09 +0000 (00:27 +0000)]
Let Geode GX2 use geode_post_code.h just like Geode LX
Also clean up gx2def.h and geode_post_code.h a little.
abuild tested and boot tested on a Wyse S50.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5671
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