Winbond W83627HF: Use existing functions instead of open-coding.

Use w83627hf_set_clksel_48() where needed instead or open-coding the same
functionality, and also use w83627hf_enable_serial() instead of
w83627hf_enable_dev() (which does exactly the same, but isn't wrapped in the
enter/exit config mode functions).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c
index 30bddde5aca854b9ffc29f0020714a70580e2924..19d4c81488ecfe8071b6057d87dcd577b1f569ed 100644 (file)
--- a/src/mainboard/msi/ms6178/romstage.c
+++ b/src/mainboard/msi/ms6178/romstage.c
@@ -33,18 +33,15 @@
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 void enable_smbus(void);
 int smbus_read_byte(u8 device, u8 address);
 
 void main(unsigned long bist)
 {
-       /* FIXME */
-       outb(0x87, 0x2e);
-       outb(0x87, 0x2e);
-       pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
+       w83627hf_set_clksel_48(DUMMY_DEV);
        w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       outb(0x87, 0xaa);
 
        uart_init();
        console_init();

diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index d11117f7d104ccdd1790db0e728060cfd27f8ec4..ff7b24f40e3ef7461f6c326296ed5f2fb84d1f26 100644 (file)
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -48,6 +48,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 
@@ -193,10 +194,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
-       pnp_enter_ext_func_mode(SERIAL_DEV);
-       pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       pnp_exit_ext_func_mode(SERIAL_DEV);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
        uart_init();
        console_init();

diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 4637392cd750d917b39ebde41a8777baca74ea35..e7875956b27c5121c6a99a3e6c8a2e175b7badf3 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -51,6 +51,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -122,10 +123,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
-       pnp_enter_ext_func_mode(SERIAL_DEV);
-        pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       pnp_exit_ext_func_mode(SERIAL_DEV);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
         uart_init();
         console_init();

diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 43d4ff7e72ba37609b13bffaf58b8a23fcde9ce6..966ae3b6948120889b9b9e30f00ee64c0ddbc107 100644 (file)
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -50,6 +50,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
@@ -125,10 +126,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x32);
 
-       pnp_enter_ext_func_mode(SERIAL_DEV);
-       pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       pnp_exit_ext_func_mode(SERIAL_DEV);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
        uart_init();
        console_init();

diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 95dd659b7f7f4062b80ee2466640b9a66ccb7039..d60350935da05281fcf7dcc5630b4b18de1a566e 100644 (file)
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -50,6 +50,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -176,10 +177,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
   post_code(0x32);
 
-       pnp_enter_ext_func_mode(SERIAL_DEV);
-       pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       pnp_exit_ext_func_mode(SERIAL_DEV);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
        uart_init();
        console_init();

diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c
index 9ae30b0e0a72ce7e2c67fe4629c7075dbd21c58b..09e52873c178f7026b15d61be31d0f378355266f 100644 (file)
--- a/src/mainboard/supermicro/x6dai_g/romstage.c
+++ b/src/mainboard/supermicro/x6dai_g/romstage.c
@@ -16,13 +16,14 @@
 #include "debug.c"
 #include "watchdog.c"
 #include "reset.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/e7525/memory_initialized.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 #define DEVPRES_CONFIG  ( \
        DEVPRES_D1F0 | \
@@ -63,11 +64,8 @@ static void main(unsigned long bist)
                        skip_romstage();
        }
 
-       /* Setup the console */
-       outb(0x87,0x2e);
-       outb(0x87,0x2e);
-       pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
 

diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index 1865a08dac05f91532c3f8772d25646844de39a8..a6dfe502a2f1666c8f3eb851330ba6e538ee5fd7 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -17,13 +17,14 @@
 #include "watchdog.c"
 #include "reset.c"
 #include "x6dhe_g_fixups.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 #define DEVPRES_CONFIG  ( \
        DEVPRES_D1F0 | \
@@ -60,11 +61,8 @@ static void main(unsigned long bist)
                        skip_romstage();
        }
 
-       /* Setup the console */
-       outb(0x87,0x2e);
-       outb(0x87,0x2e);
-       pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
 

diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index 794234ea718c60b58ac8e316fd8dc741655ae46f..19527db91835027b568d04403c4c265b45c58568 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c
@@ -15,13 +15,14 @@
 #include "watchdog.c"
 #include "reset.c"
 #include "x6dhr_fixups.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 #define DEVPRES_CONFIG  ( \
        DEVPRES_D0F0 | \
@@ -59,11 +60,8 @@ static void main(unsigned long bist)
                        skip_romstage();
        }
 
-       /* Setup the console */
-       outb(0x87,0x2e);
-       outb(0x87,0x2e);
-       pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
 

diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
index 5e54fa66fa179d7794afd89d7e9a8f05ae65f984..eb54ef563240d343866072c6775ff8eed1db9b61 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
@@ -15,13 +15,14 @@
 #include "watchdog.c"
 #include "reset.c"
 #include "x6dhr2_fixups.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 #define DEVPRES_CONFIG  ( \
        DEVPRES_D0F0 | \
@@ -59,11 +60,8 @@ static void main(unsigned long bist)
                        skip_romstage();
        }
 
-       /* Setup the console */
-       outb(0x87,0x2e);
-       outb(0x87,0x2e);
-       pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
 

diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 6d0957049becd8b3fb3cb63f30f409683b9ba43d..85522c03d97e0d28089796f5d6361e679f6dd42e 100644 (file)
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -46,6 +46,7 @@
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 /*
  * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
@@ -384,7 +385,7 @@ void main(unsigned long bist)
         */
        pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
        /* EmbedComInit(); */
-       w83697hf_set_clksel_48(SERIAL_DEV);
+       w83697hf_set_clksel_48(DUMMY_DEV);
        w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        /* enable_vx800_serial(); */

diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c
index 30ea0f2a3a253d6f0376adb221ed040ced571955..22e12cb6787a17df481d700e581e46bf678fb48c 100644 (file)
--- a/src/mainboard/via/epia-n/romstage.c
+++ b/src/mainboard/via/epia-n/romstage.c
@@ -38,6 +38,7 @@
 #include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 static const struct mem_controller ctrl = {
        .d0f0 = 0x0000,
@@ -109,7 +110,7 @@ static void main(unsigned long bist)
        /* Enable multifunction for northbridge. */
        pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
-       w83697hf_set_clksel_48(SERIAL_DEV);
+       w83697hf_set_clksel_48(DUMMY_DEV);
        w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();