2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
5 #include <arch/romcc_io.h>
6 #include <cpu/x86/lapic.h>
8 #include <console/console.h>
9 #include "pc80/udelay_io.c"
10 #include "lib/delay.c"
11 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
12 #include "northbridge/intel/e7525/raminit.h"
13 #include "superio/winbond/w83627hf/w83627hf.h"
14 #include "cpu/x86/lapic/boot_cpu.c"
15 #include "cpu/x86/mtrr/earlymtrr.c"
19 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
20 #include "northbridge/intel/e7525/memory_initialized.c"
21 #include "cpu/x86/bist.h"
24 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
25 #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
26 #define DUMMY_DEV PNP_DEV(0x2e, 0)
28 #define DEVPRES_CONFIG ( \
35 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
37 static inline int spd_read_byte(unsigned device, unsigned address)
39 return smbus_read_byte(device, address);
42 #include "northbridge/intel/e7525/raminit.c"
43 #include "lib/generic_sdram.c"
44 #include "arch/i386/lib/stages.c"
46 static void main(unsigned long bist)
48 static const struct mem_controller mch[] = {
51 .f0 = PCI_DEV(0, 0x00, 0),
52 .f1 = PCI_DEV(0, 0x00, 1),
53 .f2 = PCI_DEV(0, 0x00, 2),
54 .f3 = PCI_DEV(0, 0x00, 3),
55 .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
56 .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
61 /* Skip this if there was a built in self test failure */
63 if (memory_initialized())
67 w83627hf_set_clksel_48(DUMMY_DEV);
68 w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
72 /* MOVE ME TO A BETTER LOCATION !!! */
73 /* config LPC decode for flash memory access */
75 dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
76 if (dev == PCI_DEV_INVALID)
77 die("Missing 6300ESB?");
78 pci_write_config32(dev, 0xe8, 0x00000000);
79 pci_write_config8(dev, 0xf0, 0x00);
82 display_cpuid_update_microcode();
90 for(i = 0; i < 1; i++)
94 sdram_initialize(ARRAY_SIZE(mch), mch);
96 dump_pci_device(PCI_DEV(0, 0x00, 0));
97 // dump_bar14(PCI_DEV(0, 0x00, 0));