2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #define FAM10_SCAN_PCI_BUS 0
23 #define FAM10_ALLOCATE_IO_RANGE 1
27 #include <device/pci_def.h>
28 #include <device/pci_ids.h>
30 #include <device/pnp_def.h>
31 #include <arch/romcc_io.h>
32 #include <cpu/x86/lapic.h>
33 #include <console/console.h>
36 #include <cpu/amd/model_10xxx_rev.h>
37 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
38 #include "northbridge/amd/amdfam10/raminit.h"
39 #include "northbridge/amd/amdfam10/amdfam10.h"
40 #include "cpu/amd/model_10xxx/apic_timer.c"
41 #include "lib/delay.c"
42 #include "cpu/x86/lapic/boot_cpu.c"
43 #include "northbridge/amd/amdfam10/reset_test.c"
44 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
45 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
46 #include "cpu/x86/bist.h"
47 #include "northbridge/amd/amdfam10/debug.c"
48 #include "cpu/x86/mtrr/earlymtrr.c"
49 #include "northbridge/amd/amdfam10/setup_resource_map.c"
50 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
52 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
53 #define DUMMY_DEV PNP_DEV(0x2e, 0)
55 static inline void activate_spd_rom(const struct mem_controller *ctrl)
57 #define SMBUS_SWITCH1 0x70
58 #define SMBUS_SWITCH2 0x72
59 smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
60 smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
63 static inline int spd_read_byte(unsigned device, unsigned address)
65 return smbus_read_byte(device, address);
68 #include "northbridge/amd/amdfam10/amdfam10.h"
69 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
70 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
71 #include "resourcemap.c"
72 #include "cpu/amd/quadcore/quadcore.c"
73 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
74 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
75 #include "cpu/amd/car/post_cache_as_ram.c"
76 #include "cpu/amd/microcode/microcode.c"
77 #include "cpu/amd/model_10xxx/update_microcode.c"
78 #include "cpu/amd/model_10xxx/init_cpus.c"
79 #include "northbridge/amd/amdfam10/early_ht.c"
81 static void sio_setup(void)
86 // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
87 smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
89 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
91 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
93 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
95 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
97 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
99 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
102 static const u8 spd_addr[] = {
104 RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
105 #if CONFIG_MAX_PHYSICAL_CPUS > 1
107 RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
109 #if CONFIG_MAX_PHYSICAL_CPUS > 2
111 RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
113 RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
117 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
118 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
119 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
121 static void write_GPIO(void)
123 pnp_enter_ext_func_mode(GPIO1_DEV);
124 pnp_set_logical_device(GPIO1_DEV);
125 pnp_write_config(GPIO1_DEV, 0x30, 0x01);
126 pnp_write_config(GPIO1_DEV, 0x60, 0x00);
127 pnp_write_config(GPIO1_DEV, 0x61, 0x00);
128 pnp_write_config(GPIO1_DEV, 0x62, 0x00);
129 pnp_write_config(GPIO1_DEV, 0x63, 0x00);
130 pnp_write_config(GPIO1_DEV, 0x70, 0x00);
131 pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
132 pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
133 pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
134 pnp_exit_ext_func_mode(GPIO1_DEV);
136 pnp_enter_ext_func_mode(GPIO2_DEV);
137 pnp_set_logical_device(GPIO2_DEV);
138 pnp_write_config(GPIO2_DEV, 0x30, 0x01);
139 pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
140 pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
141 pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
142 pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
143 pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
144 pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
145 pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
146 pnp_exit_ext_func_mode(GPIO2_DEV);
148 pnp_enter_ext_func_mode(GPIO3_DEV);
149 pnp_set_logical_device(GPIO3_DEV);
150 pnp_write_config(GPIO3_DEV, 0x30, 0x00);
151 pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
152 pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
153 pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
154 pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
155 pnp_exit_ext_func_mode(GPIO3_DEV);
158 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
160 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
161 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
162 u32 bsp_apicid = 0, val, wants_reset;
165 if (!cpu_init_detectedx && boot_cpu()) {
166 /* Nothing special needs to be done to find bus 0 */
167 /* Allow the HT devices to be found */
168 set_bsp_node_CHtExtNodeCfgEn();
169 enumerate_ht_chain();
176 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
180 w83627hf_set_clksel_48(DUMMY_DEV);
181 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
186 printk(BIOS_DEBUG, "\n");
188 /* Halt if there was a built in self test failure */
189 report_bist_failure(bist);
192 printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
193 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
194 printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
195 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
197 /* Setup sysinfo defaults */
198 set_sysinfo_in_ram(0);
200 update_microcode(val);
206 amd_ht_init(sysinfo);
209 /* Setup nodes PCI space and start core 0 AP init. */
210 finalize_node_setup(sysinfo);
212 /* Setup any mainboard PCI settings etc. */
213 setup_mb_resource_map();
216 /* wait for all the APs core0 started by finalize_node_setup. */
217 /* FIXME: A bunch of cores are going to start output to serial at once.
218 * It would be nice to fixup prink spinlocks for ROM XIP mode.
219 * I think it could be done by putting the spinlock flag in the cache
220 * of the BSP located right after sysinfo.
223 wait_all_core0_started();
224 #if CONFIG_LOGICAL_CPUS==1
225 /* Core0 on each node is configured. Now setup any additional cores. */
226 printk(BIOS_DEBUG, "start_other_cores()\n");
229 wait_all_other_cores_started(bsp_apicid);
234 #if CONFIG_SET_FIDVID
235 msr = rdmsr(0xc0010071);
236 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
238 /* FIXME: The sb fid change may survive the warm reset and only
239 * need to be done once.*/
241 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
244 if (!warm_reset_detect(0)) { // BSP is node 0
245 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
247 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
252 /* show final fid and vid */
253 msr=rdmsr(0xc0010071);
254 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
257 init_timer(); // Need to use TMICT to synconize FID/VID
259 wants_reset = mcp55_early_setup_x();
261 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
262 if (!warm_reset_detect(0)) {
263 print_info("...WARM RESET...\n\n\n");
265 die("After soft_reset_x - shouldn't see this message!!!\n");
269 printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
273 /* It's the time to set ctrl in sysinfo now; */
274 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
275 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
279 //printk(BIOS_DEBUG, "enable_smbus()\n");
280 // enable_smbus(); /* enable in sio_setup */
284 printk(BIOS_DEBUG, "raminit_amdmct()\n");
285 raminit_amdmct(sysinfo);
288 // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
289 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
290 post_code(0x42); // Should never see this post code.