src/mainboard/supermicro/x6dai_g/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "pc80/udelay_io.c"
  10 #include "lib/delay.c"
  11 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
  12 #include "northbridge/intel/e7525/raminit.h"
  13 #include "superio/winbond/w83627hf/w83627hf.h"
  14 #include "cpu/x86/lapic/boot_cpu.c"
  15 #include "cpu/x86/mtrr/earlymtrr.c"
  16 #include "debug.c"
  17 #include "watchdog.c"
  18 #include "reset.c"
  19 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  20 #include "northbridge/intel/e7525/memory_initialized.c"
  21 #include "cpu/x86/bist.h"
  22 #include <spd.h>
  23
  24 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  25 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  26
  27 #define DEVPRES_CONFIG  ( \
  28         DEVPRES_D1F0 | \
  29         DEVPRES_D2F0 | \
  30         DEVPRES_D3F0 | \
  31         DEVPRES_D4F0 | \
  32         DEVPRES_D6F0 | \
  33         0 )
  34 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  35
  36 static inline int spd_read_byte(unsigned device, unsigned address)
  37 {
  38         return smbus_read_byte(device, address);
  39 }
  40
  41 #include "northbridge/intel/e7525/raminit.c"
  42 #include "lib/generic_sdram.c"
  43 #include "arch/i386/lib/stages.c"
  44
  45 static void main(unsigned long bist)
  46 {
  47         static const struct mem_controller mch[] = {
  48                 {
  49                         .node_id = 0,
  50                         .f0 = PCI_DEV(0, 0x00, 0),
  51                         .f1 = PCI_DEV(0, 0x00, 1),
  52                         .f2 = PCI_DEV(0, 0x00, 2),
  53                         .f3 = PCI_DEV(0, 0x00, 3),
  54                         .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
  55                         .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
  56                 }
  57         };
  58
  59         if (bist == 0) {
  60                 /* Skip this if there was a built in self test failure */
  61                 early_mtrr_init();
  62                 if (memory_initialized())
  63                         skip_romstage();
  64         }
  65
  66         /* Setup the console */
  67         outb(0x87,0x2e);
  68         outb(0x87,0x2e);
  69         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  70         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  71         uart_init();
  72         console_init();
  73
  74         /* MOVE ME TO A BETTER LOCATION !!! */
  75         /* config LPC decode for flash memory access */
  76         device_t dev;
  77         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  78         if (dev == PCI_DEV_INVALID)
  79                 die("Missing 6300ESB?");
  80         pci_write_config32(dev, 0xe8, 0x00000000);
  81         pci_write_config8(dev, 0xf0, 0x00);
  82
  83 #if 0
  84         display_cpuid_update_microcode();
  85         print_pci_devices();
  86 #endif
  87 #if 1
  88         enable_smbus();
  89 #endif
  90 #if 0
  91         int i;
  92         for(i = 0; i < 1; i++)
  93                 dump_spd_registers();
  94 #endif
  95         disable_watchdogs();
  96         sdram_initialize(ARRAY_SIZE(mch), mch);
  97 #if 1
  98         dump_pci_device(PCI_DEV(0, 0x00, 0));
  99 //      dump_bar14(PCI_DEV(0, 0x00, 0));
 100 #endif
 101 }