src/mainboard/supermicro/x6dhr_ig/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  10 #include "northbridge/intel/e7520/raminit.h"
  11 #include "superio/winbond/w83627hf/w83627hf.h"
  12 #include "cpu/x86/lapic/boot_cpu.c"
  13 #include "cpu/x86/mtrr/earlymtrr.c"
  14 #include "debug.c"
  15 #include "watchdog.c"
  16 #include "reset.c"
  17 #include "x6dhr_fixups.c"
  18 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  19 #include "northbridge/intel/e7520/memory_initialized.c"
  20 #include "cpu/x86/bist.h"
  21 #include <spd.h>
  22
  23 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  24 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  25 #define DUMMY_DEV PNP_DEV(0x2e, 0)
  26
  27 #define DEVPRES_CONFIG  ( \
  28         DEVPRES_D0F0 | \
  29         DEVPRES_D1F0 | \
  30         DEVPRES_D2F0 | \
  31         DEVPRES_D3F0 | \
  32         DEVPRES_D4F0 | \
  33         DEVPRES_D6F0 | \
  34         0 )
  35 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  36
  37 static inline int spd_read_byte(unsigned device, unsigned address)
  38 {
  39         return smbus_read_byte(device, address);
  40 }
  41
  42 #include "northbridge/intel/e7520/raminit.c"
  43 #include "lib/generic_sdram.c"
  44 #include "arch/i386/lib/stages.c"
  45
  46 static void main(unsigned long bist)
  47 {
  48         static const struct mem_controller mch[] = {
  49                 {
  50                         .node_id = 0,
  51                         .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
  52                         .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
  53                 }
  54         };
  55
  56         if (bist == 0) {
  57                 /* Skip this if there was a built in self test failure */
  58                 early_mtrr_init();
  59                 if (memory_initialized())
  60                         skip_romstage();
  61         }
  62
  63         w83627hf_set_clksel_48(DUMMY_DEV);
  64         w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  65         uart_init();
  66         console_init();
  67
  68         /* Halt if there was a built in self test failure */
  69 //      report_bist_failure(bist);
  70
  71         /* MOVE ME TO A BETTER LOCATION !!! */
  72         /* config LPC decode for flash memory access */
  73         device_t dev;
  74         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
  75         if (dev == PCI_DEV_INVALID)
  76                 die("Missing ich5?");
  77         pci_write_config32(dev, 0xe8, 0x00000000);
  78         pci_write_config8(dev, 0xf0, 0x00);
  79
  80 #if 0
  81         display_cpuid_update_microcode();
  82         print_pci_devices();
  83 #endif
  84 #if 1
  85         enable_smbus();
  86 #endif
  87 #if 0
  88 //      dump_spd_registers(&cpu[0]);
  89         int i;
  90         for(i = 0; i < 1; i++)
  91                 dump_spd_registers();
  92 #endif
  93         disable_watchdogs();
  94 //      dump_ipmi_registers();
  95         mainboard_set_e7520_leds();
  96         sdram_initialize(ARRAY_SIZE(mch), mch);
  97 #if 1
  98         dump_pci_devices();
  99 #endif
 100 #if 0
 101         dump_pci_device(PCI_DEV(0, 0x00, 0));
 102         dump_bar14(PCI_DEV(0, 0x00, 0));
 103 #endif
 104 }