Mark Norman [Sat, 18 Jun 2011 00:54:36 +0000 (10:24 +0930)]
Add SMSC SCH3114 superio register descriptions to superiotool.
This has been tested on a Aaeon PFM-540I RevB PC104 SBC.
Change-Id: Ie02875a1fa2d90d7cc843ce745f727312f7b7aec
Signed-off-by: Mark Norman <mpnorman@gmail.com>
Reviewed-on: http://review.coreboot.org/43
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sven Schnelle [Thu, 23 Jun 2011 11:43:52 +0000 (13:43 +0200)]
T60: undock on external power loss
If power is unplugged/lost, we should undock the docking station.
The power loss can also be caused by the fact that the user removed
the thinkpad from the docking station without pressing the Undock button/hotkey
first. Without undocking it on this event, the thinkpad LPC switch will still
connect the Docking connector, which causes crashes when docking it again.
Change-Id: I9ed783e491827bde20264868eab2b3a79c232922
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/62
Tested-by: build bot (Jenkins)
Sven Schnelle [Thu, 23 Jun 2011 11:41:55 +0000 (13:41 +0200)]
T60: enable userspace EC events
EC events 0x50-0x5f are never triggered by the EC. Instead they
can be generated by writing the wanted events to register 0x2a.
Change-Id: Ifd7ce991ee094cb16e8425ed670b6b45cffe3907
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/61
Tested-by: build bot (Jenkins)
Sven Schnelle [Thu, 23 Jun 2011 09:59:48 +0000 (11:59 +0200)]
T60: add additional EC events
We missed a few bits, i.e the battery and some hotkey events.
Change-Id: Ia5561532f421eb3b40225301f0af639112abc3cc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/60
Tested-by: build bot (Jenkins)
Sven Schnelle [Thu, 23 Jun 2011 09:15:55 +0000 (11:15 +0200)]
Add ThinkPad models
Change-Id: I4f1a5d99486929eb0be76a0ab3bf0158a23c7d36
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/59
Tested-by: build bot (Jenkins)
Sven Schnelle [Wed, 22 Jun 2011 14:08:51 +0000 (16:08 +0200)]
T60: add missing License Header
Change-Id: I03636deac7b6d8e01654cf978b1aac79cba10641
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/58
Tested-by: build bot (Jenkins)
Sven Schnelle [Wed, 22 Jun 2011 14:08:45 +0000 (16:08 +0200)]
X60: add missing License Header
Change-Id: I9d6e80a633990e86dd3adfa2a761d09f62978349
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/57
Tested-by: build bot (Jenkins)
Sven Schnelle [Wed, 22 Jun 2011 14:08:32 +0000 (16:08 +0200)]
H8: add missing License Header
Change-Id: If472e1e8bb93d64cc52a9084ad33fb9abbf0fb33
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/56
Tested-by: build bot (Jenkins)
Sven Schnelle [Wed, 22 Jun 2011 14:08:20 +0000 (16:08 +0200)]
PMH7: add missing License Header
Change-Id: I3468689408fce05142a0959d5d725bdbd03faea7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/55
Tested-by: build bot (Jenkins)
Scott Duplichan [Wed, 22 Jun 2011 01:05:19 +0000 (20:05 -0500)]
Move SB800 clock init earlier
Committing Scott's e350m1 changes (svn r6585):
Move SB800 clock init earlier,
Fixes problem where initial serial port output is garbled.
Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/32
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Cristian Măgherușan-Stanciu [Sun, 19 Jun 2011 01:03:28 +0000 (03:03 +0200)]
Add the coreboot config to CBFS
The CBFS will contain a new file, named 'config' of type 'raw' that is a
stripped-down version of the .config file that was used to build the
current coreboot image. For space savings, all the comments and empty
lines were removed from the original config, except for one that lists
the coreboot git revision that's built into the image.
This is done in order to easily reproduce the work of someone else when
only having their ROM image. In theory the reproduce could even be
automated by a new dedicated make target.
This should work even with abuild now.
Change-Id: I784989aac0227d3679d30314b06dadaec402749e
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/46
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
efdesign98 [Tue, 21 Jun 2011 01:12:43 +0000 (18:12 -0700)]
Move existing AMD Ffamily14 code to f14 folder
This change moves the AMD Family14 cpu Agesa code to
the vendorcode/amd/agesa/f14 folder to complete the
transition to the family oriented folder structure.
Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/52
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
efdesign98 [Tue, 21 Jun 2011 00:38:49 +0000 (17:38 -0700)]
Rename {CPU|NB|SB}/amd/*_wrapper folders
This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.
Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
efdesign98 [Thu, 16 Jun 2011 23:39:30 +0000 (16:39 -0700)]
Add AMD SB900 CIMx code
This code is added to support the AMD SB900 southbridge.
Change-Id: I7dc5e13a53ffd479dcea4e05e8c8631096e2ba91
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/41
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
efdesign98 [Thu, 16 Jun 2011 23:35:54 +0000 (16:35 -0700)]
Add AMD Family 12 cpu Agesa code
This is the addition of the AMD Family 12 cpu code.
Change-Id: I3febc81e192b4e86bbd3e8d6e1da62a28598fa8c
Signed-off-by: Frank Vibrans<frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/40
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Stefan Reinauer [Sat, 4 Jun 2011 17:37:35 +0000 (10:37 -0700)]
sb800: move spi prefetch and fast read mode to sb bootblock.
So we don't waste time on the first cbfs scan.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[adapt persimmon with the same change, and work around romcc bug
in bootblock code: it doesn't like MEMACCESS[idx] |= value;]
Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
Reviewed-on: http://review.coreboot.org/9
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Cristian Măgherușan-Stanciu [Sun, 19 Jun 2011 21:07:20 +0000 (21:07 +0000)]
Introduced support for 8MB and 16MB flash sizes
Change-Id: I217ff84be3575ec09781710f19ad272c88227663
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/49
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Marshall Buschman [Sat, 18 Jun 2011 17:04:41 +0000 (12:04 -0500)]
ASRock E350M1: Enable USB3 support
Requires Scott Duplichan's patch for NIC support.
Enables required PCIe port for USB3 - does not interfere
with normal operations on non-USB3 model.
Change-Id: I451bb1b4f799d6485e75fa949933e25e821b65f9
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/45
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Scott Duplichan [Sat, 18 Jun 2011 15:46:45 +0000 (10:46 -0500)]
ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic
Scott Duplichan's patch from the mailing list:
sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function
once, after determining device 0x15 function enables.
1) Update the asrock e350m1 devicetree.cb to match the hardware.
2) Change the way the sb800 cimx wrapper code works. The original
cimx code calls sb800 cimx function sbBeforePciInit() once. When
ported to coreboot, the gpp component of this function was called
once for each gpp port, as the gpp port's enable/disable state
became known. A 05/15/2011 change makes the early gpp code run
only once, triggered by processing the 4th gpp port. This method
is not general enough because the 4th gpp port is not enabled on
all boards. With the current change, the early gpp code runs when
the first gpp port is processed. If any gpp ports are enabled, the
first must be enabled. Tested with Win7 and linux on asrock e350m1.
This change will also affect amd inagua, and has not been tested
on that board.
Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/44
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Sven Schnelle [Fri, 17 Jun 2011 18:47:08 +0000 (20:47 +0200)]
SMM: flush caches after disabling caching
Fixes spurious SMI crashes i've seen, and ACPI/SMM interaction.
For reference, the mail i've sent to ML with the bugreport:
whenever i've docked/undocked the thinkpad from the docking station,
i had to do that twice to get the action actually to happen.
First i thought that would be some error in the ACPI code. Here's a
short explanation how docking/undocking works:
1) ACPI EC Event 0x37 Handler is executed (EC sends event 0x37 on dock)
2) _Q37 does a Trap(SMI_DOCK_CONNECT). Trap is declared as follows:
a) Store(Arg0, SMIF) // SMIF is in the GNVS Memory Range
b) Store(0, 0x808) // Generates I/O Trap to SMM
c) // SMM is executed
d) Return (SMIF) // Return Result in SMIF
I've verified that a) is really executed with ACPI debugging in the
Linux Kernel. It writes the correct value to GNVS Memory. After that,
i've logged the SMIF value in SMM, which contains some random (or
former) value of SMIF.
So i've added the GNVS area to /proc/mtrr which made things work.
I've also tried a wbinvd() in SMM code, with the same result.
After reading the src/cpu/x86/smm/smmhandler.S code, i've recognized
that it starts with:
movw $(smm_gdtptr16 - smm_handler_start +
SMM_HANDLER_OFFSET), %bx
data32 lgdt %cs:(%bx)
movl %cr0, %eax
andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
orl $0x60000001, %eax /* CD, NW, PE = 1 */
movl %eax, %cr0
/* Enable protected mode */
data32 ljmp $0x08, $1f
...which disables caching in SMM code, but doesn't flush the cache.
So the problem is:
- the linux axpi write to the SMIF GNVS Area will be written to Cache,
because GNVS is WB
- the SMM code runs with cache disabled, and fetches SMIF directly from
Memory, which is some other value
Possible Solutions:
- enable cache in SMM (yeah, cache poisoning...)
- flush caches in SMM (really expensive)
- mark GNVS as UC in Memory Map (will only work if OS
really marks that Area as UC. Checked various vendor BIOSes, none
of them are marking NVS as UC. So this seems rather uncommon.)
- flush only the cache line which contains GNVS. Would fix this
particular problem, but users/developers could see other Bugs like
this. And not everyone likes to debug such problems. So i won't like
this solution.
Change-Id: Ie60bf91c5fd1491bc3452d5d9b7fc8eae39fd77a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/39
Tested-by: build bot (Jenkins)
Sven Schnelle [Fri, 17 Jun 2011 19:26:28 +0000 (21:26 +0200)]
T60: set dock LED's in mainboard.c
The docking takes place in romstage to have early serial I/O for debugging.
But to keep romstage small and prevent linking the EC code to romstage, set the
status LED's in ramstage.
Change-Id: I89fadbd61b6bfd9aff8c22370e51c84325f24751
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/42
Tested-by: build bot (Jenkins)
Sven Schnelle [Thu, 16 Jun 2011 14:43:46 +0000 (16:43 +0200)]
X60/T60: disable USB power during suspend
Change-Id: I11afba5d7531132a0274e55e8a478985a0ef956f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/38
Tested-by: build bot (Jenkins)
Sven Schnelle [Thu, 16 Jun 2011 14:43:04 +0000 (16:43 +0200)]
Lenovo H8 EC: add usb_power_enable()
Can be used to disable/enable Power output on USB ports.
Change-Id: I5eb52b33c9e3359b0e5874bda2c0c8d75c196bc2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/37
Tested-by: build bot (Jenkins)
Sven Schnelle [Tue, 14 Jun 2011 18:55:54 +0000 (20:55 +0200)]
SMM: don't overwrite SMM memory on resume
Overwriting the SMM Area on resume leaves us with
all variables cleared out, i.e., the GNVS pointer
is no longer available, which makes SMIF function
calls impossible.
Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/34
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sven Schnelle [Sun, 12 Jun 2011 12:30:10 +0000 (14:30 +0200)]
i945 GMA: restore tft brightness from cmos
Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/24
Tested-by: build bot (Jenkins)
Sven Schnelle [Wed, 15 Jun 2011 15:13:27 +0000 (17:13 +0200)]
Remove old ACPI code
it isn't used anywhere, and could be fetched from git/svn history if
needed.
Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/35
Tested-by: build bot (Jenkins)
Sven Schnelle [Wed, 15 Jun 2011 07:26:34 +0000 (09:26 +0200)]
i82801gx: replace
cafed00d/
cafebabe by defines
We're using '0xcafed00d' all over the code as magic for ACPI S3
resume. Let's add a define for that. Also replace 0xcafebabe by
a define.
Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/33
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Stefan Reinauer [Fri, 10 Jun 2011 18:05:53 +0000 (20:05 +0200)]
Update README with newer version of the text from the web page
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I4f181979ca5e47b27731c681a320b34cbecc0027
Reviewed-on: http://review.coreboot.org/19
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Sven Schnelle [Sun, 12 Jun 2011 14:49:13 +0000 (16:49 +0200)]
X60: handle EC events in SMM if ACPI is disabled
Change-Id: I0fee890bd2d667b54965201f5c90da3656d7af5c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/27
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sven Schnelle [Sun, 12 Jun 2011 12:35:11 +0000 (14:35 +0200)]
X60: trigger save cmos on volume/brightness change
Change-Id: I020e06bc311c4e4327c9d3cf2c379dc8fe070a7a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/25
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sven Schnelle [Mon, 6 Jun 2011 13:58:54 +0000 (15:58 +0200)]
CMOS: add set_option()
Change-Id: I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/23
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Sven Schnelle [Sun, 12 Jun 2011 13:08:58 +0000 (15:08 +0200)]
X60/T60: set CMOS defaults
Change-Id: I5789a03898cdbade67887c0389aab5c773f867d9
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/26
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Marshall Buschman [Sat, 11 Jun 2011 02:16:41 +0000 (21:16 -0500)]
ASRock/E350M1: Skip memory clear for boot time reduction
Applying Scott's patches to e350m1, svn r6600:
Memory clear is not required for non-ECC boards.
Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/20
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Sven Schnelle [Sun, 12 Jun 2011 14:55:56 +0000 (16:55 +0200)]
X60/T60: fix return value of mainboard_io_trap_handler()
The handler should return 1 if it handled the request. The current
code returns 0, which causes 'Unknown function' logs.
Change-Id: Ic296819a5f8c6f1f97b7d47148182226684882a0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/29
Tested-by: build bot (Jenkins)
Sven Schnelle [Sun, 12 Jun 2011 14:53:25 +0000 (16:53 +0200)]
log ec data with DEBUG_SPEW
Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/28
Tested-by: build bot (Jenkins)
Jonathan A. Kollasch [Wed, 8 Jun 2011 15:18:43 +0000 (10:18 -0500)]
Add ACPI automatic PIC/APIC interrupt routing logic for ck804
Change-Id: I2d462ca1220ea31af243c7a58a1dc33c39e9c840
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/13
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Uwe Hermann [Thu, 9 Jun 2011 18:56:29 +0000 (20:56 +0200)]
superiotool: Cosmetics and coding style fixes.
Change-Id: Iacda2a9e37635d5cffc5004caf588ef3e5e09b5e
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Reviewed-on: http://review.coreboot.org/18
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Sven Schnelle [Sun, 5 Jun 2011 18:47:49 +0000 (20:47 +0200)]
H8 EC: add volume CMOS setting
Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/12
Tested-by: build bot (Jenkins)
Peter Stuge [Thu, 9 Jun 2011 03:04:20 +0000 (05:04 +0200)]
util/crossgcc: Add build-without-gdb Makefile target
Change-Id: I5d02f1a23e54aa67be0cc01d921898c28c22f8e4
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/16
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
Peter Stuge [Thu, 9 Jun 2011 02:54:16 +0000 (04:54 +0200)]
util/crossgcc: Add buildgcc -G and --skip-gdb options
Change-Id: Ic31130774ad56abf0b5498b04b4890348352a621
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/15
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
Peter Stuge [Thu, 9 Jun 2011 03:06:25 +0000 (05:06 +0200)]
Change make crossgcc to build without gdb by default
Using gdb with coreboot is not (yet) very common, so at least for
now it makes sense to not build gdb by default. A make crosstools
target is also added, which runs the full build in util/crossgcc
and thus generates a toolchain with both compiler and debugger.
Change-Id: I939ebcd06ae9a1bc485fd18e70cac98112d3bbbf
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/17
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
Marc Jones [Wed, 8 Jun 2011 20:41:52 +0000 (14:41 -0600)]
Revert changes to set the sb800 to AHCI mode.
Seabios doesn't have this support included yet,
which causes the generic Persimmon and other CIMx
sb800 platforms to not boot.
Change-Id: If07328b7c62d7fc314647adce8fab983ed327854
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/14
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Cristian Măgherușan-Stanciu [Tue, 7 Jun 2011 12:55:40 +0000 (14:55 +0200)]
Add basic .gitignore
Ignore directories created by abuild, jenkins, payloads and crossgcc.
Change-Id: I7d4145fc1e54a10ffdc4b884d8b8f0ae53e615c6
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/10
Tested-by: build bot (Jenkins)
Sven Schnelle [Sun, 5 Jun 2011 19:32:51 +0000 (21:32 +0200)]
T60/PMH7: move 'touchpad' option to pmh7
This option is PMH7 specific, and should be moved there,
so all Notebook utilizing a PMH7 have this option.
For Thinkpads without Touchpad (like the X60), simply
don't add 'touchpad' to cmos.layout.
Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/6
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sven Schnelle [Sun, 5 Jun 2011 09:39:12 +0000 (11:39 +0200)]
i82801gx: enable ACPI during S3 resume
disabling ACPI during S3 wakeup breaks ACPI wakeup, as the
Host OS is assuming that ACPI is enabled.
Change-Id: I8ced72c4b553d41a57f26d64998118e8a77621f8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/7
Tested-by: build bot (Jenkins)
Sven Schnelle [Sun, 5 Jun 2011 09:33:41 +0000 (11:33 +0200)]
SMM: add defines for APM_CNT register
in the current code, the defines for the APM_CNT (0xb2) register
are duplicated in almost every place where it is used. define those
values in cpu/x86/smm.h, and only include this file.
And while at it, fixup whitespace.
Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/4
Tested-by: build bot (Jenkins)
Patrick Georgi [Sun, 5 Jun 2011 13:15:49 +0000 (15:15 +0200)]
Add "gitconfig" make target to simplify gerrit configuration
"make gitconfig" installs the gerrit commit-msg hook and validates
that user.name and user.email are configured.
No data will be overwritten.
Change-Id: I49ec98538574866e7ad6238ff3d02b9c1beef1bb
Reviewed-on: http://review.coreboot.org/2
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Sven Schnelle [Sun, 5 Jun 2011 18:43:04 +0000 (20:43 +0200)]
T60: fix touchpad option
Code used 'int' as return type, but the cmos option is only one
bit. get_option returned with the value in bit 0-7, but all remaining
bits were left unitialized by get_option(). fix this by using char
as type.
Change-Id: I60e609164277380f936f66c99ef9508fa6a6b67c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/5
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Stefan Reinauer [Sat, 4 Jun 2011 17:36:21 +0000 (10:36 -0700)]
re-indent, so files conform to coding guidelines.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab
Reviewed-on: http://review.coreboot.org/8
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Sven Schnelle [Sat, 4 Jun 2011 17:35:22 +0000 (19:35 +0200)]
SMM: add mainboard_apm_cnt() callback
motherboards can use this hook to get notified if someone writes
to the APM_CNT port (0xb2). If the hook returns 1, the chipset
specific hook is also skipped.
Change-Id: I05f1a27cebf9d25db8064f2adfd2a0f5759e48b5
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/3
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Patrick Georgi [Fri, 3 Jun 2011 19:56:13 +0000 (21:56 +0200)]
Teach abuild to emit JUnit formatted build reports
Jenkins can produce reports from JUnit test cases, so we fake testcases
for each board.
Change-Id: I34d46d15c83f4f04d2228f302eb626b261ac098d
Reviewed-on: http://review.coreboot.org/1
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Stefan Reinauer [Sat, 4 Jun 2011 16:30:27 +0000 (16:30 +0000)]
WARNINGS_ARE_ERRORS is y per default, don't set it twice.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6637
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:48:14 +0000 (15:48 +0000)]
Port persimmon r6594 to e350m1: Cosmetic cleanup
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6636
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:47:56 +0000 (15:47 +0000)]
Port persimmon r6593 to e350m1: Remove unused Kconfig options
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6635
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:47:30 +0000 (15:47 +0000)]
Port persimmon r6592 to e350m1: Update GPP port configuration
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6634
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:47:05 +0000 (15:47 +0000)]
Port persimmon r6591 to e350m1: ROM cache early
Enable rom cache early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:46:50 +0000 (15:46 +0000)]
Port persimmon r6590 to e350m1: Work around memory allocation problem
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6632
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:46:32 +0000 (15:46 +0000)]
Port persimmon r6589 to e350m1: Strip down AGESA options
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6631
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:46:13 +0000 (15:46 +0000)]
Port persimmon r6588 to e350m1: VGA framebuffer
Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6630
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:45:46 +0000 (15:45 +0000)]
Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6629
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:45:29 +0000 (15:45 +0000)]
Port persimmon r6586 to e350m1: FADT revision
Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6628
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:45:12 +0000 (15:45 +0000)]
Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:44:54 +0000 (15:44 +0000)]
Port persimmon r6583 to e350m1: pstate 0 early
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:44:31 +0000 (15:44 +0000)]
Port persimmon r6582 to e350m1: 33 MHz SPI read early
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6625
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:44:14 +0000 (15:44 +0000)]
Port persimmon r6578 and r6596 to e350m1: MMCONF base
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6624
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:43:56 +0000 (15:43 +0000)]
Port persimmon r6574 to e350m1: MMCONF size
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6623
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:43:38 +0000 (15:43 +0000)]
Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from
dfffffff to
fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6622
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marshall Buschman [Sat, 4 Jun 2011 15:43:15 +0000 (15:43 +0000)]
Port persimmon r6572 to e350m1: I/O APIC ID
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6621
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sat, 4 Jun 2011 15:40:12 +0000 (15:40 +0000)]
vt8237r: Simplify bootblock init to work around nested if() romcc problem
During the hackathon in Prague we discovered that romcc has a problem
compiling the previous nested if() statements correctly. This patch
makes the code a little simpler, and indeed works around the romcc issue.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6620
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marc Jones [Fri, 3 Jun 2011 19:59:52 +0000 (19:59 +0000)]
This patch sets max freq defaults for ddr2 and ddr3for fam10.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Alexandru Gagniuc [Fri, 3 Jun 2011 19:46:25 +0000 (19:46 +0000)]
Correct wrong PCI ID for VIA K8M890 Chrome.
With the K8T800/M800 patch from r6367 the PCI IDs for the VIA chrome were
moved to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly.
(3220 instead of 3230). This patch defines the correct PCI ID for this device.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6618
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Fri, 3 Jun 2011 10:14:56 +0000 (10:14 +0000)]
advansus/a785e-i mainboard enable warning as error
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6617
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Wed, 1 Jun 2011 19:54:16 +0000 (19:54 +0000)]
Really fix iasl filename issues in our build system
There's a remaining issue that iasl cuts of "\..*$" from
output paths, even if that substring contains "/" (ie.
across directories)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6616
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Wed, 1 Jun 2011 19:29:48 +0000 (19:29 +0000)]
Report build result from abuild (did all requested boards build?)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6615
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Wed, 1 Jun 2011 02:00:30 +0000 (02:00 +0000)]
trivial remove blanks at the end of line
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6614
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Wed, 1 Jun 2011 01:56:49 +0000 (01:56 +0000)]
This patch fix a AMD sb800 wrapper compile warning:
src/southbridge/amd/cimx_wrapper/sb800/late
call clear_ioapic but not include the prototype declare header file.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 23 May 2011 22:48:13 +0000 (22:48 +0000)]
We don't have pausing versions of single-IO instructions.
Hence remove the wrong comment.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6612
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 23 May 2011 22:43:43 +0000 (22:43 +0000)]
AP_IN_SIPI_WAIT is already defined in the CPU Kconfig of those boards.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6611
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Mon, 23 May 2011 17:55:20 +0000 (17:55 +0000)]
Correct implementation of r6608.
(.align actually takes its argument in bytes)
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6610
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 23 May 2011 17:16:44 +0000 (17:16 +0000)]
exclude src/vendorcode from GPLv2 license checks.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6609
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Sun, 22 May 2011 15:39:25 +0000 (15:39 +0000)]
Ensure ck804 romstrap is 16-byte aligned.
This alignment seems to be necessary for the chip to recognize it.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6608
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Sat, 21 May 2011 22:18:59 +0000 (22:18 +0000)]
Add regression test for build directory handling to make lint target
A couple of scenarios that were fixed in the last few revisions are
tested to ensure that it's easy to determine breakage.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6607
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 20 May 2011 23:31:41 +0000 (23:31 +0000)]
Handle absolute source file paths
We used to fail there because we unconditionally prefixed the relative directory where it was referenced.
Tested in various scenarios:
- obj=build
- obj=../obj
- obj=$PWD/../obj
- obj=/some/other/absolute/path
- obj=/./some/other/absolute/path
In-tree relative paths still work as before, the only change in behaviour is when a source file name (as specified in one of the *-y variables) starts with "/".
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6606
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 20 May 2011 23:08:12 +0000 (23:08 +0000)]
Handle both cases, obj being absolute and relative
gnu make's handling of filenames is less than optimal. It simply
compares strings, so foo/../bar is different from bar, even though
they're logically the same.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6605
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 20 May 2011 22:17:58 +0000 (22:17 +0000)]
Fix building with relative path to object directory outside the source tree
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6604
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 20 May 2011 22:16:49 +0000 (22:16 +0000)]
iasl still can't cope with extra "." in file paths
It's really a work around, but given how this issue seems to come
back again and again, let's work around it.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6603
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Fri, 20 May 2011 22:14:07 +0000 (22:14 +0000)]
Fix ccache behaviour if more than one ccache in PATH
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6602
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Fri, 20 May 2011 17:50:14 +0000 (17:50 +0000)]
Correct amd persimmon romstage code for early SPI prefetch enable.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Fri, 20 May 2011 00:06:09 +0000 (00:06 +0000)]
Move the ACPI FACP table to the front of the RSDT list. This is done to work around a Windows XP or Server 2003 setup failure where an error message such as: "An unexpected error (
805262864) occurred at line 1768 of d:\xpclient\base\boot\setup\arcdisp.c" occurs. This change updates AMD reference board projects, but could applied to others as well.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6600
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Mon, 16 May 2011 15:32:28 +0000 (15:32 +0000)]
Move crossgcc rules to coreboot specific Makefile
Toplevel Makefile should (as far as possible) be coreboot-agnostic,
we have Makefile.inc for that.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6599
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Cristian Magherusan-Stanciu [Mon, 16 May 2011 01:35:03 +0000 (01:35 +0000)]
Add crossgcc target to automatically build reference toolchain
This means that a simple:
$ make crossgcc
creates the reference toolchain in the correct directory. Thanks to the
dependency on the clean-for-update target, an existing .xcompile along
with any compiled objects in build/ will be cleaned out, so the next
build will automatically use the newly created reference toolchain.
Signed-off-by: Cristian Magherusan-Stanciu <cristi.magherusan@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6598
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Mon, 16 May 2011 00:05:50 +0000 (00:05 +0000)]
cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6597
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marc Jones [Sun, 15 May 2011 23:13:54 +0000 (23:13 +0000)]
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6596
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Sun, 15 May 2011 22:40:40 +0000 (22:40 +0000)]
agesa_wrapper: Avoid repetitive Kconfig depends, trivial
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6595
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:10:15 +0000 (22:10 +0000)]
Cosmetic cleanup.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:09:09 +0000 (22:09 +0000)]
1) Remove unused kconfig options.
2) Correct UMA graphics PCI device ID.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:07:56 +0000 (22:07 +0000)]
Update gpp port configuration.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:06:09 +0000 (22:06 +0000)]
Enable rom cache early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6591
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:05:00 +0000 (22:05 +0000)]
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6590
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 15 May 2011 22:03:45 +0000 (22:03 +0000)]
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6589
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1