sb800: move spi prefetch and fast read mode to sb bootblock.

So we don't waste time on the first cbfs scan.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[adapt persimmon with the same change, and work around romcc bug
 in bootblock code: it doesn't like MEMACCESS[idx] |= value;]

Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
Reviewed-on: http://review.coreboot.org/9
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>

diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 3f2aa1032917469d8bc24eedd466a2791b27f6dd..5ef5557a5b842f6948385631aefdcfed24bac8b6 100644 (file)
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -70,26 +70,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
     *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
     }
 
-  // early enable of PrefetchEnSPIFromHost
-  if (boot_cpu())
-    {
-    __outdword (0xcf8, 0x8000a3b8);
-    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
-    }
-
-  // early enable of SPI 33 MHz fast mode read
-  if (boot_cpu())
-    {
-    volatile u32 *spiBase = (void *) 0xa0000000;
-    u32 save;
-    __outdword (0xcf8, 0x8000a3a0);
-    save = __indword (0xcfc);
-    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
-    spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
-    spiBase [0] |= 1 << 18; // fast read enable
-    __outdword (0xcfc, save); // clear temp base
-    }
-
   if (!cpu_init_detectedx && boot_cpu()) {
     post_code(0x30);
     sb_poweron_init();

diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 7d25ec1d384d6017eeb1e512a5492b527307516f..61de9f6ee8c2e69b97bae51a1d484ba744754c3a 100644 (file)
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -55,23 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
        __writemsr(0xc0010062, 0);
 
-       // early enable of PrefetchEnSPIFromHost
-       if (boot_cpu()) {
-               __outdword(0xcf8, 0x8000a3b8);
-               __outdword(0xcfc, __indword(0xcfc) | 1 << 24);
-       }
-       // early enable of SPI 33 MHz fast mode read
-       if (boot_cpu()) {
-               volatile u32 *spiBase = (void *)0xa0000000;
-               u32 save;
-               __outdword(0xcf8, 0x8000a3a0);
-               save = __indword(0xcfc);
-               __outdword(0xcfc, (u32) spiBase | 2);   // set temp MMIO base
-               spiBase[3] = (spiBase[3] & ~(3 << 14)) | (1 << 14);
-               spiBase[0] |= 1 << 18;  // fast read enable
-               __outdword(0xcfc, save);        // clear temp base
-       }
-
        if (!cpu_init_detectedx && boot_cpu()) {
                post_code(0x30);
                sb_poweron_init();

diff --git a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
index 9d8a349c6ea960d9cb886aa6e760831ef9da01c6..aaec03cbea4507095f54387c78dca5feac36673c 100644 (file)
--- a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
@@ -20,9 +20,9 @@
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 
-static void sb800_enable_rom(void)
+static void enable_rom(void)
 {
-       u32 word;
+       u16 word;
        u32 dword;
        device_t dev;
 
@@ -56,8 +56,39 @@ static void sb800_enable_rom(void)
        pci_io_write_config16(dev, 0x6c, word);
 }
 
+static void enable_prefetch(void)
+{
+       u32 dword;
+       device_t dev = PCI_DEV(0, 0x14, 0x03);
+
+       /* Enable PrefetchEnSPIFromHost */
+       dword = pci_io_read_config32(dev, 0xb8);
+       pci_io_write_config32(dev, 0xb8, dword | (1 << 24));
+}
+
+static void enable_spi_fast_mode(void)
+{
+       u8 byte;
+       u32 dword;
+       device_t dev = PCI_DEV(0, 0x14, 0x03);
+
+       // set temp MMIO base
+       volatile u32 *spi_base = (void *)0xa0000000;
+       u32 save = pci_io_read_config32(dev, 0xa0);
+       pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2);
+
+       // early enable of SPI 33 MHz fast mode read
+       byte = spi_base[3];
+       spi_base[3] = (byte & ~(3 << 14)) | (1 << 14);
+       spi_base[0] = spi_base[0] | (1 << 18);  // fast read enable
+
+       pci_io_write_config32(dev, 0xa0, save);
+}
+
 static void bootblock_southbridge_init(void)
 {
        /* Setup the rom access for 2M */
-       sb800_enable_rom();
+       enable_rom();
+       enable_prefetch();
+       enable_spi_fast_mode();
 }