remove trailing whitespace
[coreboot.git] / src / northbridge / amd / amdmct / mct_ddr3 /
2011-10-15 Stefan ReinauerAMD CPU and chipset fixes for compilation with gcc 4.6
2011-06-03 Marc JonesThis patch sets max freq defaults for ddr2 and ddr3for...
2011-01-20 Zheng BaoFor Cx, each ChipSel need to be sent MR command.
2011-01-17 Zheng BaoThe code is tested on my board with register DIMMs...
2011-01-06 Zheng BaoFix some settings fo AMD MCT. It is based on BIOS test...
2010-12-02 Zheng BaoMore explicite and straight way to set seed.
2010-10-13 Zheng BaoTrivial. Clean up code and add some comments.
2010-10-09 Zheng BaoTrivial. Spell checking.
2010-10-09 Zheng BaoTrivial. Spell checking.
2010-10-08 Zheng BaoTrivial. Spell checking.
2010-10-08 Zheng BaoTrivial. Fix the typo.
2010-10-01 Zheng BaoTrivial. Re-indent the code.
2010-09-28 Zheng BaoTrivial. re-Indent the code.
2010-09-27 Xavi Drudis FerranObviously missing brackets.
2010-09-21 Zheng BaoFix the typo. Field DisAutoRefresh is in DramTimngHi.
2010-09-09 Arne Georg GleditschAlso improve boot time on AMD for the DDR3 code path.
2010-09-05 Zheng BaoTrivial. Currently the max frequency is preset as 400Mh...
2010-09-04 Kerry SheAMD DDR2 and DDR3 MCT function InitPhyCompensation...
2010-08-31 Zheng BaoGet Byte65/66 for register manufacture ID code. RegMan1...
2010-08-30 Kerry SheMulti-DIMMS on AMD ddr3 MCT channel B works.
2010-08-30 Kerry SheTrivial syntax correction of AMD mct_ddr3 dir.
2010-08-22 Xavi Drudis Ferrandocumented workaround erratum 414, see
2010-08-22 Xavi Drudis Ferrandocumented workaround erratum 372, see
2010-04-23 Zheng BaoDDR3 support for AMD Fam10.