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(parent: fe6c2cd) | patch
DDR3 support for AMD Fam10.
authorZheng Bao <zheng.bao@amd.com>
Fri, 23 Apr 2010 17:32:48 +0000 (17:32 +0000)
committerStefan Reinauer <stepan@openbios.org>
Fri, 23 Apr 2010 17:32:48 +0000 (17:32 +0000)
commiteb75f652d392d2f4f257194e112f3f0db7479145
treeaa972907734abcba4ca52f2a3a71f8d81d4bdce0tree | snapshot
parentfe6c2cda6e6977894d9b668af9509b983c850f68commit | diff
DDR3 support for AMD Fam10.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
31 files changed:
src/northbridge/amd/amdfam10/amdfam10.h diff | blob | history
src/northbridge/amd/amdfam10/raminit_amdmct.c diff | blob | history
src/northbridge/amd/amdmct/amddefs.h diff | blob | history
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctprob.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctproc.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctrci.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mctwl.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mport_d.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c [new file with mode: 0644] blob
src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h [new file with mode: 0644] blob
src/northbridge/amd/amdmct/wrappers/mcti_d.c diff | blob | history
my coreboot WIP stuff (asus m5a99x-evo board)