Print a warning when an unknow USB controller type is detected.

The Intel E6XX Atom processor reports an unknown USB controller type (in
addition to the standard EHCI and OHCI ones).  Add a default case to
print a warning when an unknown controller type is detected.

Change-Id: I885d0ccec4c46fd212cceac599290e9bf85edbbb
Signed-off-by: Steven A. Falco <sfalco@coincident.com>
Reviewed-on: http://review.coreboot.org/100
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Move AMD SB800 early clock setup.

Move the AMD SB800 early clock setup code that is needed for early
serial port operation from mainboard/romstage.c to sb800/bootblock.c.
This prevents code duplication and simplifies porting.

Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/96
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

EHCI driver missing bus_address assignment.

Other USB drivers set the bus_address field.  EHCI should do this too.

Signed-off-by: Steven A. Falco <sfalco@coincident.com>
Change-Id: Ic4274c6744951ef7fa0cb135caf8b9f177d8bcaf
Reviewed-on: http://review.coreboot.org/99
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Set SB800 ROM decode size based on kconfig.

Change-Id: I46ea26b5534064fe1c7e2ce2b2f12cacf18a4d4d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/94
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Enable SMI on M2V-MX SE

Finally the SMI routines are in good shape on AMD, lets enable this and later
implement ACPI on/off SMI commands.

Change-Id: I9848a7be908780353eead30c16fd2df8ea48f77e
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/83
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Make AMD SMM SMP aware

Move the SMM MSR init to a code run per CPU. Introduce global SMM_BASE define,
later all 0xa0000 could be changed to use it. Remove the unnecessary test if
the smm_init routine is called once (it is called by BSP only) and also remove
if lock bit is set becuase this bit is cleared by INIT it seems.
Add the defines for fam10h and famfh to respective files, we do not have any
shared AMD MSR header file.

Tested on M2V-MX SE with dualcore CPU.

Change-Id: I1b2bf157d1cc79c566c9089689a9bfd9310f5683
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/82
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Do full flush on uart8250 only at end of printk.

The previous code does a full flush of the uart after every character.
Unfortunately, this can cause transmission delays on some serial
ports.

This patch changes the code so that it does a flush at the end of
every printk instead of at the end of every character.  This reduces
the time it takes to transmit serial messages (up to 9% on my Asrock
e350m1 board).  It also makes the transmission time more consistent
which is important when performing timing tests via serial
transmissions.

Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-on: http://review.coreboot.org/90
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Sven Schnelle <svens@stackframe.org>

libpayload: Add qsort()

It's taken from OpenBSD and thus appropriately licensed (and reasonably
tested).

Change-Id: I5767600c9865d39e56c220b52e045f3501875b98
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/88
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

T60: enable GPIO before using GPIO I/O port range

Change-Id: I39369e6f8a39f53f58a4b7fbe357637a79f5b596
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/93
Tested-by: build bot (Jenkins)

T60: dont use X60 USB init flag

ec byte 0x03, bit 2 seems to be only used on the X60s for USB switch
initialization. Don't touch it on T60.

Change-Id: Icb89a514757a0e06ccea200fde62a778fa8c268e
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/92
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)

ASRock E350M1: ACPI-related BSOD fix

On installing/starting Windows (tested with Win7 Ultimate)
the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error.

From Scott Duplichan:
To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT
must be corrected. The attached patch does this. It uses the older
patching method, and not the (possibly preferred) AML generation
method. To simplify the patching operation, I moved the AML item
'TOM1' to the start of the SSDT. The patch also includes code to
confirm the AML variable TOM1 is at the expected offset before patching.

Also tested & working with Linux.

Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/91
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Fix memory size reporting on AMD family 14h systems for >= 4GB

Applying Scott Duplichan's fix for memory >=4GB

Adjusted it to the new directory structure (agesa_wrapper was renamed to
just agesa).

Boot-tested and confirmed to work, on my board Linux can now access the
whole RAM.

Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/48
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

libpayload: Don't declare mouse support in tinycurses

Change-Id: Id1ff3d85617e3ec063ce332cf13920dfbbb7cf26
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/87
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: Provide atol(), malloc.h

Change-Id: I807ca061115146a6851eef481eb881b279fba8e1
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/86
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: Implement strlcpy

Change-Id: Ibd339957690afe2cded46895c3088eba87f0ffd1
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/85
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: fix wborder()

wborder didn't provide default characters to draw a border.

Change-Id: Ib746ed16be341598fd9fa1f1b7577606d1abd9e5
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/84
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix lint-002-build-dir-handling

That lint test requires some Kconfig defaults and uses allyesconfig
for that. Unfortunately that also draws in ccache and scanbuild support,
which significantly change the behaviour of the toplevel Makefile.
Notably, the ccache support breaks if no ccache is installed.

Change-Id: I17cbb7974be33fc077e5cbd5fb616a5b00a47d97
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/80
Tested-by: build bot (Jenkins)

T60: handle EC events in SMM if ACPI is disabled

Change-Id: I6f9e90015cafef3da896453ef8e3588434ae3554
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/89
Tested-by: build bot (Jenkins)

Run 'git fetch' in SeaBIOS only when really needed

This allows coreboot to compile without Internet connectivity

Change-Id: I969471e44e417f127fdc8744e868211500acee3e
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/11
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Small SMM fixups

Align the spinlock to the 4 byte boundary (CPU will guarantee atomicity of XCHG).
While at it add the PAUSE instruction to spinlock loop to hint the CPU we are just
spinlocking. The rep nop could not be used because "as" complains that rep is used
without string instructions.

Change-Id: I325cd83de3a6557b1bee6758bc151bc81e874f8c
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/81
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Fixes to the libpayload build system

- its Makefile is part of the libpayload project
- fix conversion bug in powerpc's Makefile.inc

Change-Id: I84f2da092c3733ea7d0f232cb3768078cf13dfd5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/79
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

whitespace-only changes in acpi.c, replaced spaces with tabs

Change-Id: Ibd598813bec0c93d77afbce8aee330498afbe5f6
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/74
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)

added a config option for ACPI debugging

Change-Id: Ie6296f5652196c6258aa6902d84dd86c17e224cb
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/36
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)

Relicense Makefile to match libpayload

libpayload's license is more liberal than coreboot's. If we are to
use the coreboot build system for libpayload (bringing a couple of
new features to libpayload), we should adopt it for this shared part
even if not strictly necessary.

Change-Id: I1349616861e193b3e01407debbec3d82e09e72c2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/70
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>

Add local copy of commit-msg hook

To avoid using untrusted network to download code, copy the
relevant file to the repo and adapt "make gitconfig" to copy
from there.

Change-Id: I21f0b58d59250aa5d795cf289267ad93bd8d74db
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/73
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
Tested-by: build bot (Jenkins)

Reduce warnings/errors in libpayload when using picky compiler options

The new build system uses quite a few more -W flags for the compiler by
default than the old one. And that's for the better.

Change-Id: Ia8e3d28fb35c56760c2bd0983046c7067e8c5dd6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/72
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

Use coreboot build system for libpayload, too.

This change makes building coreboot related projects more unified.

Change-Id: I0f1181e2fffde1e03675523f7dc9eef3119052c3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/71
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP and
for the transmit clock driving control. Unfortunately this is not enough
to make the HT1000 work reliably, therefore blacklist this for now in CPU
HT code. If ever anyone figure out what is wrong, it could be removed. The
downgrading now makes the board work on HT800, which is certainly better than
not at all with a HT1000 CPU.

Change-Id: I949bfd9b0b48ee12bd0234c2fb1deaaa773bd235
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/68
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Added support for Aaeon PFM-540I RevB PC104 SBC

The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU.
More infomation about the board available at www.aaeon.com.

Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd
Signed-off-by: Mark Norman <mpnorman@gmail.com>
Reviewed-on: http://review.coreboot.org/30
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

i82801gx: read RTC status register to prevent IRQ storm

My Thinkpad appeared dead. After investigation, it turned out
that the RTC Alarm was triggering an RTC PM1 SMI, but the SMI
handler didn't read the status register, so it was triggered again.

This is a really nasty situation, as it means you have to dissemble
your Notebook just to unplug the RTC battery.

Change-Id: I5ac611e8a72deb5f38c86486dbe0693804935723
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/67
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Libpayload needs to clear the bss region.

Libpayload shouldn't count on coreboot or other payloads to clear memory. This fixes problems with payloads being loaded after or on top of each other.

Change-Id: I30303d47e465e8921f47acab667c7998ba79fca7
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/66
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

amd southbirdge sb800 wrapper, pci bridge fix

sb800 pci bridge SHOULD enabled by default according to the chipset document,
but actually not enabled on some mainboard.
enable sb800 pci bridge when told to enable in devicetree.cb.
tested on ibase persimmon mainboard.

Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/63
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Add the AMD Torpedo mainboard

The Torpedo mainboard is the reference platform for
the AMD Family 12 cpus and the AMD Hudson-2 (SB900)
southbridge.

Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/54
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Addition of Family12/SB900 wrapper code

This change adds the wrapper code for the AMD Family12
cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
northbridge and southbridge folders respectively.

Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/53
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

msrtool: added support for Intel CPUs

Change-Id: I05f54471665aa99335a88d097c6de20174f91dc6
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/50
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

SMM: add guard and include types.h in cpu/x86/smm.h

Change-Id: I002845cf7a37cd6885456131826ae0ba681823ef
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/64
Tested-by: build bot (Jenkins)

X60: remove pci config register save/restore

SMM code already makes sure this register is saved and restored,
so we don't have to do it.

Change-Id: I078e1227de4436fba9c5fb3879a564c981cb0f9a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/65
Tested-by: build bot (Jenkins)

Add SMSC SCH3114 superio register descriptions to superiotool.

This has been tested on a Aaeon PFM-540I RevB PC104 SBC.

Change-Id: Ie02875a1fa2d90d7cc843ce745f727312f7b7aec
Signed-off-by: Mark Norman <mpnorman@gmail.com>
Reviewed-on: http://review.coreboot.org/43
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

T60: undock on external power loss

If power is unplugged/lost, we should undock the docking station.
The power loss can also be caused by the fact that the user removed
the thinkpad from the docking station without pressing the Undock button/hotkey
first. Without undocking it on this event, the thinkpad LPC switch will still
connect the Docking connector, which causes crashes when docking it again.

Change-Id: I9ed783e491827bde20264868eab2b3a79c232922
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/62
Tested-by: build bot (Jenkins)

T60: enable userspace EC events

EC events 0x50-0x5f are never triggered by the EC. Instead they
can be generated by writing the wanted events to register 0x2a.

Change-Id: Ifd7ce991ee094cb16e8425ed670b6b45cffe3907
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/61
Tested-by: build bot (Jenkins)

T60: add additional EC events

We missed a few bits, i.e the battery and some hotkey events.

Change-Id: Ia5561532f421eb3b40225301f0af639112abc3cc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/60
Tested-by: build bot (Jenkins)

Add ThinkPad models

Change-Id: I4f1a5d99486929eb0be76a0ab3bf0158a23c7d36
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/59
Tested-by: build bot (Jenkins)

T60: add missing License Header

Change-Id: I03636deac7b6d8e01654cf978b1aac79cba10641
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/58
Tested-by: build bot (Jenkins)

X60: add missing License Header

Change-Id: I9d6e80a633990e86dd3adfa2a761d09f62978349
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/57
Tested-by: build bot (Jenkins)

H8: add missing License Header

Change-Id: If472e1e8bb93d64cc52a9084ad33fb9abbf0fb33
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/56
Tested-by: build bot (Jenkins)

PMH7: add missing License Header

Change-Id: I3468689408fce05142a0959d5d725bdbd03faea7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/55
Tested-by: build bot (Jenkins)

Move SB800 clock init earlier

Committing Scott's e350m1 changes (svn r6585):
Move SB800 clock init earlier,
Fixes problem where initial serial port output is garbled.

Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/32
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Add the coreboot config to CBFS

The CBFS will contain a new file, named 'config' of type 'raw' that is a
stripped-down version of the .config file that was used to build the
current coreboot image. For space savings, all the comments and empty
lines were removed from the original config, except for one that lists
the coreboot git revision that's built into the image.

This is done in order to easily reproduce the work of  someone else when
only having their ROM image. In theory the reproduce could even be
automated by a new dedicated make target.

This should work even with abuild now.

Change-Id: I784989aac0227d3679d30314b06dadaec402749e
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/46
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Move existing AMD Ffamily14 code to f14 folder

This change moves the AMD Family14 cpu Agesa code to
the vendorcode/amd/agesa/f14 folder to complete the
transition to the family oriented folder structure.

Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/52
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Rename {CPU|NB|SB}/amd/*_wrapper folders

This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.

Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Add AMD SB900 CIMx code

This code is added to support the AMD SB900 southbridge.

Change-Id: I7dc5e13a53ffd479dcea4e05e8c8631096e2ba91
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/41
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Add AMD Family 12 cpu Agesa code

This is the addition of the AMD Family 12 cpu code.

Change-Id: I3febc81e192b4e86bbd3e8d6e1da62a28598fa8c
Signed-off-by: Frank Vibrans<frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/40
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

sb800: move spi prefetch and fast read mode to sb bootblock.

So we don't waste time on the first cbfs scan.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[adapt persimmon with the same change, and work around romcc bug
 in bootblock code: it doesn't like MEMACCESS[idx] |= value;]

Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
Reviewed-on: http://review.coreboot.org/9
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>

Introduced support for 8MB and 16MB flash sizes

Change-Id: I217ff84be3575ec09781710f19ad272c88227663
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/49
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

ASRock E350M1: Enable USB3 support

Requires Scott Duplichan's patch for NIC support.
Enables required PCIe port for USB3 - does not interfere
with normal operations on non-USB3 model.

Change-Id: I451bb1b4f799d6485e75fa949933e25e821b65f9
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/45
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic

Scott Duplichan's patch from the mailing list:
sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function
once, after determining device 0x15 function enables.

1) Update the asrock e350m1 devicetree.cb to match the hardware.
2) Change the way the sb800 cimx wrapper code works. The original
cimx code calls sb800 cimx function sbBeforePciInit() once. When
ported to coreboot, the gpp component of this function was called
once for each gpp port, as the gpp port's enable/disable state
became known. A 05/15/2011 change makes the early gpp code run
only once, triggered by processing the 4th gpp port. This method
is not general enough because the 4th gpp port is not enabled on
all boards. With the current change, the early gpp code runs when
the first gpp port is processed. If any gpp ports are enabled, the
first must be enabled. Tested with Win7 and linux on asrock e350m1.
This change will also affect amd inagua, and has not been tested
on that board.

Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/44
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>

SMM: flush caches after disabling caching

Fixes spurious SMI crashes i've seen, and ACPI/SMM interaction.
For reference, the mail i've sent to ML with the bugreport:

whenever i've docked/undocked the thinkpad from the docking station,
i had to do that twice to get the action actually to happen.

First i thought that would be some error in the ACPI code. Here's a
short explanation how docking/undocking works:

1) ACPI EC Event 0x37 Handler is executed (EC sends event 0x37 on dock)
2) _Q37 does a Trap(SMI_DOCK_CONNECT). Trap is declared as follows:

   a) Store(Arg0, SMIF) // SMIF is in the GNVS Memory Range
   b) Store(0, 0x808)   // Generates I/O Trap to SMM
   c) // SMM is executed
   d) Return (SMIF)    // Return Result in SMIF

I've verified that a) is really executed with ACPI debugging in the
Linux Kernel. It writes the correct value to GNVS Memory. After that,
i've logged the SMIF value in SMM, which contains some random (or
former) value of SMIF.

So i've added the GNVS area to /proc/mtrr which made things work.
I've also tried a wbinvd() in SMM code, with the same result.

After reading the src/cpu/x86/smm/smmhandler.S code, i've recognized
that it starts with:

        movw    $(smm_gdtptr16 - smm_handler_start +
        SMM_HANDLER_OFFSET), %bx
        data32  lgdt %cs:(%bx)

        movl    %cr0, %eax
        andl    $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
        orl     $0x60000001, %eax /* CD, NW, PE = 1 */
        movl    %eax, %cr0

        /* Enable protected mode */
        data32  ljmp    $0x08, $1f

...which disables caching in SMM code, but doesn't flush the cache.

So the problem is:

- the linux axpi write to the SMIF GNVS Area will be written to Cache,
  because GNVS is WB
- the SMM code runs with cache disabled, and fetches SMIF directly from
  Memory, which is some other value

Possible Solutions:

- enable cache in SMM (yeah, cache poisoning...)

- flush caches in SMM (really expensive)

- mark GNVS as UC in Memory Map (will only work if OS
  really marks that Area as UC. Checked various vendor BIOSes, none
  of them are marking NVS as UC. So this seems rather uncommon.)

- flush only the cache line which contains GNVS. Would fix this
  particular problem, but users/developers could see other Bugs like
  this. And not everyone likes to debug such problems. So i won't like
  this solution.

Change-Id: Ie60bf91c5fd1491bc3452d5d9b7fc8eae39fd77a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/39
Tested-by: build bot (Jenkins)

T60: set dock LED's in mainboard.c

The docking takes place in romstage to have early serial I/O for debugging.
But to keep romstage small and prevent linking the EC code to romstage, set the
status LED's in ramstage.

Change-Id: I89fadbd61b6bfd9aff8c22370e51c84325f24751
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/42
Tested-by: build bot (Jenkins)

X60/T60: disable USB power during suspend

Change-Id: I11afba5d7531132a0274e55e8a478985a0ef956f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/38
Tested-by: build bot (Jenkins)

Lenovo H8 EC: add usb_power_enable()

Can be used to disable/enable Power output on USB ports.

Change-Id: I5eb52b33c9e3359b0e5874bda2c0c8d75c196bc2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/37
Tested-by: build bot (Jenkins)

SMM: don't overwrite SMM memory on resume

Overwriting the SMM Area on resume leaves us with
all variables cleared out, i.e., the GNVS pointer
is no longer available, which makes SMIF function
calls impossible.

Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/34
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

i945 GMA: restore tft brightness from cmos

Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/24
Tested-by: build bot (Jenkins)

Remove old ACPI code

it isn't used anywhere, and could be fetched from git/svn history if
needed.

Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/35
Tested-by: build bot (Jenkins)

i82801gx: replace cafed00d/cafebabe by defines

We're using '0xcafed00d' all over the code as magic for ACPI S3
resume. Let's add a define for that. Also replace 0xcafebabe by
a define.

Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/33
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Update README with newer version of the text from the web page

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I4f181979ca5e47b27731c681a320b34cbecc0027
Reviewed-on: http://review.coreboot.org/19
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-by: Sven Schnelle <svens@stackframe.org>

X60: handle EC events in SMM if ACPI is disabled

Change-Id: I0fee890bd2d667b54965201f5c90da3656d7af5c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/27
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

X60: trigger save cmos on volume/brightness change

Change-Id: I020e06bc311c4e4327c9d3cf2c379dc8fe070a7a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/25
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

CMOS: add set_option()

Change-Id: I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/23
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

X60/T60: set CMOS defaults

Change-Id: I5789a03898cdbade67887c0389aab5c773f867d9
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/26
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

ASRock/E350M1: Skip memory clear for boot time reduction

Applying Scott's patches to e350m1, svn r6600:
Memory clear is not required for non-ECC boards.

Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/20
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

X60/T60: fix return value of mainboard_io_trap_handler()

The handler should return 1 if it handled the request. The current
code returns 0, which causes 'Unknown function' logs.

Change-Id: Ic296819a5f8c6f1f97b7d47148182226684882a0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/29
Tested-by: build bot (Jenkins)

log ec data with DEBUG_SPEW

Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/28
Tested-by: build bot (Jenkins)

Add ACPI automatic PIC/APIC interrupt routing logic for ck804

Change-Id: I2d462ca1220ea31af243c7a58a1dc33c39e9c840
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/13
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

superiotool: Cosmetics and coding style fixes.

Change-Id: Iacda2a9e37635d5cffc5004caf588ef3e5e09b5e
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Reviewed-on: http://review.coreboot.org/18
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

H8 EC: add volume CMOS setting

Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/12
Tested-by: build bot (Jenkins)

util/crossgcc: Add build-without-gdb Makefile target

Change-Id: I5d02f1a23e54aa67be0cc01d921898c28c22f8e4
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/16
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>

util/crossgcc: Add buildgcc -G and --skip-gdb options

Change-Id: Ic31130774ad56abf0b5498b04b4890348352a621
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/15
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>

Change make crossgcc to build without gdb by default

Using gdb with coreboot is not (yet) very common, so at least for
now it makes sense to not build gdb by default. A make crosstools
target is also added, which runs the full build in util/crossgcc
and thus generates a toolchain with both compiler and debugger.

Change-Id: I939ebcd06ae9a1bc485fd18e70cac98112d3bbbf
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/17
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>

Revert changes to set the sb800 to AHCI mode.

Seabios doesn't have this support included yet,
which causes the generic Persimmon and other CIMx
sb800 platforms to not boot.

Change-Id: If07328b7c62d7fc314647adce8fab983ed327854
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/14
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Add basic .gitignore

Ignore directories created by abuild, jenkins, payloads and crossgcc.

Change-Id: I7d4145fc1e54a10ffdc4b884d8b8f0ae53e615c6
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/10
Tested-by: build bot (Jenkins)

T60/PMH7: move 'touchpad' option to pmh7

This option is PMH7 specific, and should be moved there,
so all Notebook utilizing a PMH7 have this option.
For Thinkpads without Touchpad (like the X60), simply
don't add 'touchpad' to cmos.layout.

Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/6
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

i82801gx: enable ACPI during S3 resume

disabling ACPI during S3 wakeup breaks ACPI wakeup, as the
Host OS is assuming that ACPI is enabled.

Change-Id: I8ced72c4b553d41a57f26d64998118e8a77621f8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/7
Tested-by: build bot (Jenkins)

SMM: add defines for APM_CNT register

in the current code, the defines for the APM_CNT (0xb2) register
are duplicated in almost every place where it is used. define those
values in cpu/x86/smm.h, and only include this file.

And while at it, fixup whitespace.

Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/4
Tested-by: build bot (Jenkins)

Add "gitconfig" make target to simplify gerrit configuration

"make gitconfig" installs the gerrit commit-msg hook and validates
that user.name and user.email are configured.

No data will be overwritten.

Change-Id: I49ec98538574866e7ad6238ff3d02b9c1beef1bb
Reviewed-on: http://review.coreboot.org/2
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

T60: fix touchpad option

Code used 'int' as return type, but the cmos option is only one
bit. get_option returned with the value in bit 0-7, but all remaining
bits were left unitialized by get_option(). fix this by using char
as type.

Change-Id: I60e609164277380f936f66c99ef9508fa6a6b67c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/5
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

re-indent, so files conform to coding guidelines.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab
Reviewed-on: http://review.coreboot.org/8
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>

SMM: add mainboard_apm_cnt() callback

motherboards can use this hook to get notified if someone writes
to the APM_CNT port (0xb2). If the hook returns 1, the chipset
specific hook is also skipped.

Change-Id: I05f1a27cebf9d25db8064f2adfd2a0f5759e48b5
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/3
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)

Teach abuild to emit JUnit formatted build reports

Jenkins can produce reports from JUnit test cases, so we fake testcases
for each board.

Change-Id: I34d46d15c83f4f04d2228f302eb626b261ac098d
Reviewed-on: http://review.coreboot.org/1
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

WARNINGS_ARE_ERRORS is y per default, don't set it twice.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Port persimmon r6594 to e350m1: Cosmetic cleanup

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Port persimmon r6593 to e350m1: Remove unused Kconfig options

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Port persimmon r6592 to e350m1: Update GPP port configuration

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Port persimmon r6591 to e350m1: ROM cache early

Enable rom cache early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Port persimmon r6590 to e350m1: Work around memory allocation problem

Fix memory allocation problem in amdInitLate. Disabled until further debug.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Port persimmon r6589 to e350m1: Strip down AGESA options

Remove some non-essential agesa options to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Port persimmon r6588 to e350m1: VGA framebuffer

Declare legacy video frame buffer so that Windows generic VGA driver will work.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible

Declare RTC as not PIIX4 compatible to match AMD hardware.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Port persimmon r6586 to e350m1: FADT revision

Make fadt revision match its length. Solves Windows 7 checked build assert.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Port persimmon r6584 and r6601 to e350m1: SPI prefetch early

Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Port persimmon r6583 to e350m1: pstate 0 early

Switch processor cores to pstate 0 early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1